Intel 440GX AGPset
Design Guide
Intel440GX AGPset Design Guide
Contents
6.4
Dimm Solution With FET Switches
System Bus Clock Layout 6.3
6.5
Thermals / Cooling Solutions 20.1
PIIX4E Power And Ground Pins
ISA and X-Bus Signals
82371EB PIIX4E
Voltage Regulator Control Silicon
IntelPentiumII Processor LAI Issue
FET Switches4 DIMM/FET Design
Intel440GX AGPset Platform Reference Design
Solution Space for Single Processor Design Based on Results
Example ATX Placement for a UP Pentium II processor
Example NLX Placement for a UP Intel Pentium II processor
Solution Space for Single Processor Designs With Single-End
Intel Pentium II Processor and Intel 440GX AGPset 100 MHz
Tables
Intel Pentium II Processor and Intel 440GX AGPset
Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs
Revision History
Date Revision Description
Intel440GX AGPset Design Guide
Introduction
Page
Introduction
About This Design Guide
References
Intel Pentium II Processor / Intel 440GX AGPset Overview
Intel Pentium II Processor
Intel 440GX AGPset
VCR
System Bus Interface
Dram Interface
Accelerated Graphics Port Interface
PCI Interface
Wired for Management Initiative
PCI-to-ISA/IDE Xcelerator PIIX4E
System Clocking
Remote Service Boot
Instrumentation
Voltage Definitions
Power Management
Design Recommendations
Remote Wake-Up
General Design Recommendations
Introduction
Motherboard Design
Page
Major Signal Sections 82443GX Top View
BGA Quadrant Assignment
ATX Form Factor
Board Description
NLX Form Factor
Four Layer Board Stack-up
Routing Guidelines
Single Processor Design
1 GTL+ Description
2 GTL+ Layout Recommendations
Single Processor Network Topology and Conditions
Single Processor Recommended Trace Lengths
Recommended Trace Lengths for Single Processor Design
Trace Minimum Length Maximum Length
Dual Processor Network Topology and Conditions
Dual Processor Systems
Single Processor Systems-Single-End Termination SET
Dual Processor Recommended Trace Lengths
SET Trace Length Requirements
SET Trace Length Requirements
Additional Guidelines
Minimizing Crosstalk
Practical Considerations
Design Methodology
Performance Requirements
12. GTL+ Design Process
Simulation Methodology
Topology Definition
Pre-Layout Simulation Sensitivity Analysis
Recommended 100 MHz System Flight Time Specs
Placement & Layout
Post-Layout Simulation
Crosstalk and the Multi-Bit Adjustment Factor
Validation
Flight Time Measurement
Signal Quality Measurement
Edge Guideline @ Processor Edge Spec @ Processor Core
Timing Analysis
Term Description
Timing Term Intel Pentium II Processor Intel 440GX AGPset
10. Recommended 100 MHz System Timing Parameters
11. Recommended 100 MHz System Flight Time Specs
Timing Term Value
AGP Layout and Routing Guidelines
AGP Connector Up Option Layout Guidelines
Connector
12. Data and Associated Strobe
13. Source Synchronous Motherboard Recommendations
14. Control Signal Line Length Recommendations
On-board AGP Compliant Device Down Option Layout Guidelines
WidthSpace Trace Line Length Line Length Matching
16. Control Signal Line Length Recommendations
Compliant 82443GX Graphics Data Routing Device
15. Source Synchronous Motherboard Recommendations
82443GX Memory Subsystem Layout and Routing Guidelines
1 100 MHz 82443GX Memory Array Considerations
To 82443GX MDs & MECCs To DIMM10 DQs To DIMM32 DQs
Register
Matching the Reference Planes
Adding Additional Decoupling Capacitor
Register Data Control Clock
Memory Layout & Routing Guidelines
Trace Width vs. Trace Spacing
18. FET Switch DQ Route Example
Switch 16212 Dimm Module
82443GX 0.6 0.4 0.6 0.4 Dimm Module
82443GX Dimm Module
24. Motherboard Model-DQMB1,5, 4 DIMMs
19. Motherboard Model SRASB#, 4 DIMMs
20. Motherboard Model SCASA#, 4 DIMMs
21. Motherboard Model SCASB#, 4 DIMMs
22. Motherboard Model WEA#, 4 DIMMs
23. Motherboard Model WEB#, 4 DIMMs
24. Motherboard Model MAA140, 4 DIMMs
25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs
3 4 Dimm Routing Guidelines no FET
PCI Bus Routing Guidelines
VCC3
Decoupling Guidelines Intel 440GX AGPset Platform
Host Bridge Controller 492 BGA
System Bus Clock Layout
Intel 440GX AGPset Clock Layout Recommendations
Clock Routing Spacing
014 018 Clock
Net Trace Length Min Max Cap
PCI Clock Layout
Sdram Clock Layout
440GX Ckbf Dlko
AGP Clock Layout
Net Trace Length Min Max Card Trace
Design Checklist
Page
Overview
Pull-up and Pull-down Resistor Values
Intel Pentium II Processor Checklist
Slot Connectivity Sheet 1
Processor Pin Pin Connection
Slot Connectivity Sheet 2
GND & Power Pin Definition
Slot Connectivity Sheet 3
Vtt VCC3 Reserved NC Vcc
Intel Pentium II Processor Signals
Intel Pentium II Processor Clocks
Design Checklist
Slot 1 Decoupling Capacitors
Uni-Processor UP Slot 1 Checklist
Dual-Processor DP Slot 1 Checklist
Voltage Regulator Module, VRM
Processor Frequency Select
Intel 440GX AGPset Clocks
1 CK100 100 MHz Clock Synthesizer
SEL100/66#
Ckbf Sdram 1 to 18 Clock Buffer
Gcke and Dclkwr Connection
82443GX Host Bridge
1 82443GX Interface
GX Connectivity Sheet 1
GX Connectivity Sheet 2
GX Connectivity Sheet 3
2 82443GX GTL+ Bus Interface
3 82443GX PCI Interface
VTTA, Vttb
Signal Description Register Pulled to ‘0’ Pulled to ‘1’
4 82443GX AGP Interface
Strapping Options
Sdram Connections
82443GX Pins/Connection Dimm Pins Pin Function
Intel 440GX AGPset Memory Interface
Sdram Connectivity
Dimm Solution With FET Switches
Registered Sdram
PIIX4E Connections
Signal Names Connection
82371EB PIIX4E
PIIX4E Connectivity Sheet 1
PIIX4E Connectivity Sheet 2
PIIX4E Connectivity Sheet 3
PIIX4E Connectivity Sheet 4
Cabling
Signal Resistor
IDE Routing Guidelines
Motherboard
Pin32,34
Reset#
PDD150 PDA20
IDE
PCI Bus Signals
PIIX4E Power And Ground Pins
PIIX4E PWR & GND
10. Non-PIIX4E PCI Signals
ISA Signals
ISA and X-Bus Signals
11. Non-PIIX4E ISA Signals
USB Interface
IDE Interface
12. Non-PIIX4E IDE
Flash Design Considerations
Flash Design
Dual-Footprint Flash Design
PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40
XD70
13. Flash Vpp Recommendations
Write Protection
System and Test Signals
Power Management Signals
VCC3
Power Button Implementation
Miscellaneous
17 82093AA Ioapic
18.1 Max1617 Temperature Sensor
Manageability Devices
18.2 LM79 Microprocessor System Hardware Monitor
18.3 82558B LOM Checklist
Pin Number Pin Name Resistor Value Comment
Required in both a and B stepping designs
Software/BIOS
USB and Multi-processor Bios
Wake On LAN WOL Header
Thermals / Cooling Solutions
Mechanicals
Design Considerations
Electricals
Routing and Board Fabrication
Layout Checklist
Applications and Add-in Hardware
Design Consideration
Debug Recommendations
Page
Logic Analyzer Interface LAI
Slot 1 Test Tools
Debug/Simulation Tools
In-Target Probe ITP
Bus Functional Model BFM
Debug Features
Intel Pentium II Processor LAI Issue
4 I/O Buffer Models
430 ohm
150 330 ohm
Kohm
150 ohm
Debug Logic Recommendations
A20M# 150 330 ohm
PICD0# 150 ohm PICD1#
Debug Considerations
Debug Procedures
Debug Layout
Design Considerations
Debug Recommendations
Third Party Vendors
Page
GTL+ Bus Slot 1 Terminator Cards
Slot 1 Connector
Processors
Supplier Contact Phone
Voltage Regulator Modules
Voltage Regulator Modules
Voltage Regulator Control Silicon
Voltage Regulator Control Silicon Vendors
Intel 440GX AGPset
Power Management Components
FET Switches4 DIMM/FET Design
Clock Drivers
Other Processor Components
Reference Design Schematics
Page
Intel 440GX AGPset Platform Reference Design
82443GX Component System bus and Dram Interfaces
VRM
Power Connectors Front Panel Jumpers