Design Checklist

3.3.2Intel® Pentium® II Processor Clocks

•Include a circuit for the system bus clock to core frequency ratio to the processor. The ratio should be configurable as opposed to hard wired. The bus frequency select straps will be latched on the rising edge of CRESET#.

•CRESET# is used as the selection signal for muxing A20M#, IGNNE#, INTR, and NMI with the processor bus/core frequency selection jumpers. A ‘244 buffer maybe used as a mux. The outputs of the ‘244 device are fed to open collector buffers for voltage translation to the CPU. See the reference board schematics for specific implementation.

•PICCLK must be driven by a clock even if an I/O APIC is not being used. This clock can be as high as 33.3 MHz in a UP system. A DP system utilizing Intel’s I/O APIC (82093AA) has a maximum PICCLK frequency of 16.666 MHz.

3.3.3Intel® Pentium® II Processor Signals

•Dual termination (56 ohm) to Vtt of the GTL+ bus is required if the trace length restrictions of a SET (single-ended termination) environment cannot be met.

•THERMTRIP# must be pulled-up to Vcc2.5 (150 ohm to 10K ohm) if used by system logic. The signal may be wire-OR’ed and does not require an external gate. It may be left as NC if it is not used. See the Debug Recommendations for further information that may affect the resistor values.

•The FERR# output must be pulled up to Vcc2.5 (150 ohm to 10K ohm) and connected to the PIIX4E. The reference schematics uses 220 ohms. See the Debug Recommendations for further information that may affect these resistor values.

•PICD[1:0]# must have 150 ohm pull-ups to Vcc2.5 even if an I/O APIC is not being used. See the Debug Recommendations for further information that may affect these resistor values.

•All CMOS inputs should be pulled up to Vcc2.5 (150 ohm to 10K ohm). See the Debug Recommendations for further information that may affect these resistor values.

•Be sure the Slot 1 inputs are not being driven by 3.3V or 5V logic. Logic translation of 3.3V or 5V signals may be accomplished by using open-drain drivers pulled-up to Vcc2.5.

•The PWRGOOD input should be driven to the appropriate level from the active-high “AND”

of the Power-Good signals from the 5V, 3.3V and VccCORE supplies. The output of any logic used to drive PWRGOOD should be a Vcc2.5 level to the processor.

•No VREF should be generated for the Intel® Pentium® II processor. VREF is locally generated on the processor card.

•Vtt must have adequate bulk decoupling based on the reaction time of the regulator used to

generate Vtt. It must provide for a current ramp of up to 8A/uS while maintaining the voltage tolerance defined in the Intel® Pentium® II Processor datasheet.

•If an on-board voltage regulator is used instead of a VRM, VccCORE must have adequate bulk decoupling based on the reaction time of the regulator used to generate VccCORE. It must provide for a current ramp of up to 30A/uS while maintaining the VRM 8.2 DC-DC Converter Specification.

•The VID lines should have pull-up resistors ONLY if they are required by the Voltage Regulator Module or on board regulator that you have chosen. The pull-up voltage used should be to the regulator input voltage (5V or 12V). However, if 12V is used, a resistor divider should be utilized to lower the VID signal to CMOS/TTL levels. The VID signals may be used to detect the presence of a processor core. A pull-up is not required unless the VID signals are

Intel®440GX AGPset Design Guide

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Intel 440GX manual Intel Pentium II Processor Clocks, Intel Pentium II Processor Signals
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440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
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