Intel 440GX manual Timing Analysis, Motherboard Layout and Routing Guidelines

Motherboard Layout and Routing Guidelines

2.7Timing Analysis

To determine the available flight time window perform an initial timing analysis. Analysis of setup and hold conditions will determine the minimum and maximum flight time bounds for the host bus. Use the following equations to establish the system flight time limits.

Table 2-7. Intel® Pentium® II Processor and Inte® l 440GX AGPset System Timing Equations

Driver	Receiver				Equation
Pentium®II	AGPset	Tflight,min	≥ Thold	− Tco,min	+ Tskew,CLK + Tskew,PCB + Tclk ,max
processor
		Tflight ,max	≤ Tcycle − Tco,max − Tsu − Tskew,CLK − Tskew,PCB − Tjit − Tadj + Tclk,min
AGPset	Pentium®II	Tflight,min	≥ Thold	− Tco,min	+ Tskew,CLK + Tskew,PCB − Tclk ,min
	processor
		Tflight,max	≤ Tcycle	− Tco,max − Tsu − Tskew,CLK − Tskew,PCB		− Tjit	− Tadj − Tclk ,max
Pentium®II	Pentium®II	Tflight ,min	≥ Thold − Tco,min		+ Tskew,CLK + Tskew,PCB
processor	processor
		Tflight ,max	≤ Tcycle	− Tco,max − Tsu − Tskew,CLK − Tskew,PCB		− Tjit	− Tadj

The terms used in the equations are described in Table 2-8.

Table 2-8. Intel® Pentium® II Processor and Intel® 440GX AGPset System Timing Terms

Term	Description
Tcycle	System cycle time. Defined as the reciprocal of the frequency
Tflight,min	Minimum system flight time. Flight time is defined in Section 4, “Debug Recommendations” on
	page 4-1.
Tflight,max	Maximum system flight time. Flight time is defined in Section 4, “Debug Recommendations” on
	page 4-1.
Tco,max	Maximum driver delay from input clock to output data.
Tco,min	Minimum driver delay from input clock to output data.
Tsu	Minimum setup time. Defined as the time for which the input data must be valid prior to the input
	clock.
Th	Minimum hold time. Defined as the time for which the input data must remain valid after the input
	clock.
Tskew,CLK	Clock generator skew. Defined as the maximum delay variation between output clock signals
	from the system clock generator.
Tskew,PCB	PCB skew. Defined as the maximum delay variation between clock signals due to system board
	variation and Intel®440GX AGPset loading variation.
Tjit	Clock jitter. Defined as the maximum edge to edge variation in a given clock signal.
	Multi-bit timing adjustment factor. This term accounts for the additional delay that occurs in the
Tadj	network when multiple data bits switch in the same cycle. The adjustment factor includes such
	mechanisms as package and PCB crosstalk, high inductance current return paths, and
	simultaneous switching noise.
Tclk,min	Minimum clock substrate delay. Defined as the minimum adjustment factor that accounts for the
	delay of the clock trace on the Pentium II processor substrate.
Tclk,max	Minimum clock substrate delay. Defined as the maximum adjustment factor that accounts for the
	delay of the clock trace on the Pentium II processor substrate.

Intel®440GX AGPset Design Guide 2-17