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Intel 440GX manual 13. Flash Vpp Recommendations, Design Checklist, Write Protection

Models: 440GX

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Design Checklist

(WP# pin not available on 8-Mbit 44-lead PSOP. In this package, treat as if the WP# pin is internally tied low, effectively eliminating the last row of the table below.)

•Use either A16 or A17 inversion for both the 2Mbit or 4Mbit to differentiate between recovery and normal modes.

•If migrating a BV design to the lower cost B5 device, Application Brief AB-65 “Migrating SmartVoltage Boot Block Flash Designs to Smart 5 Flash” is available (Order#292194).

Table 3-13. Flash Vpp Recommendations

VPP	RP#	WP#	Write Protection

VIL	X	X	All Blocks Locked (Programming)

≥ VPPLK	VIL	X	All Blocks Locked (All operations)

≥ VPPLK	VHH	X	All Blocks Unlocked (All operations)

≥ VPPLK	VIH	VIL	Boot Block Locked (Programming)

≥ VPPLK	VIH	VIH	All Blocks Unlocked (All operations)

NOTES:

1.VPPLK is specified at 1.5V(maximum).

2.VIL is specified at logic low.

3.VIH is specified at logic high.

4.VHH is specified at 12V±5%.

•Use SUSA# to drive the flash RP# pin into the deep power-down mode when system is in the suspend states.

•(SUSA# Alternative) Use system “POWEROK” or “POWERGOOD” signal to drive flash RP# to keep device in deep power down during power-up only (write protection). For systems not needing power saving modes.

•Connect BYTE# to GND for byte-wide mode operation if x16 device is used.

•Use a 0.01mf - 0.1mf ceramic capacitor connected between each Vcc and GND, and between its Vpp and GND. These high frequency, inherently low inductance capacitors should be placed as close as possible to the package leads.

•Add information on how BIOSCS# elevates the need for control logic and GPO[x] control on WE#

•Add information on ISA load consideration and the reduction of the X-bus drivers/control

Figure 3-7illustrates the recommended layout for Intel’s flash devices in desktop designs:

Intel®440GX AGPset Design Guide

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Intel 440GX manual 13. Flash Vpp Recommendations, Design Checklist, Write Protection

Contents

Design Guide Intel 440GX AGPsetMarch Intel440GX AGPset Design Guide Contents Validation 82371EB PIIX4E 4.3.1 IntelPentiumII Processor LAI Issue Figures Tables Revision Revision HistoryIntel440GX AGPset Design Guide DateIntel440GX AGPset Design Guide Introduction Page Introduction 1.1 About This Design GuideIntroduction AP-589 EMI WWW order number 1.2 ReferencesIntel 440GX AGPset Datasheet WWW order number Introduction1.3 Intel Pentium II Processor / Intel 440GX AGPset Overview 1.3.1 Intel Pentium II ProcessorIntroduction Introduction 1.3.2 Intel 440GX AGPsetIntroduction 1.3.2.1 System Bus Interface1.3.2.2 DRAM Interface 1.3.2.3 Accelerated Graphics Port Interface1.3.2.5 System Clocking 1.3.4 Wired for Management Initiative1.3.3 PCI-to-ISA/IDE Xcelerator PIIX4E 1.3.2.4 PCI Interface1.3.3.2 Remote Service Boot 1.3.3.1 InstrumentationIntroduction 1.3.3.3 Remote Wake-Up 1.3.3.4 Power Management1.4 Design Recommendations 1.4.1 Voltage DefinitionsIntroduction 1.4.2 General Design Recommendations1.4.3 Transitioning from Intel 440BX AGPset to Intel 440GX AGPset DesignIntel440GX AGPset Design Guide IntroductionMotherboard Design Page 2.1 BGA Quadrant Assignment Figure 2-1. Major Signal Sections 82443GX Top ViewMotherboard Layout and Routing GuidelinesATX Form Factor Motherboard Layout and Routing Guidelines2.2 Board Description Motherboard Layout and Routing GuidelinesNLX Form Factor Motherboard Layout and Routing Guidelines Figure 2-4. Four Layer Board Stack-upMotherboard Layout and Routing Guidelines 2.3 Routing Guidelines2.3.3.1 Single Processor Network Topology and Conditions 2.3.1 GTL+ Description2.3.2 GTL+ Layout Recommendations 2.3.3 Single Processor Design2.3.3.2 Single Processor Recommended Trace Lengths Table 2-1. Recommended Trace Lengths for Single Processor DesignMotherboard Layout and Routing Guidelines 2.3.4.2 Dual Processor Recommended Trace Lengths 2.3.4 Dual Processor Systems2.3.5 Single Processor Systems-Single-End Termination SET 2.3.4.1 Dual Processor Network Topology and Conditions2.3.5.2 SET Trace Length Requirements Table 2-3. SET Trace Length RequirementsMotherboard Layout and Routing Guidelines Motherboard Layout and Routing Guidelines 2.3.6 Additional Guidelines2.3.6.1 Minimizing Crosstalk 2.3.6.2 Practical ConsiderationsMotherboard Layout and Routing Guidelines 2.3.7 Design Methodology2.3.8 Performance Requirements Figure 2-12. GTL+ Design ProcessMotherboard Layout and Routing Guidelines Table 2-4. Recommended 100 MHz System Flight Time Specs 2.3.9 Topology Definition2.3.10 Pre-Layout Simulation Sensitivity Analysis 2.3.11 Simulation MethodologyMotherboard Layout and Routing Guidelines 2.4 Placement & Layout2.5 Post-Layout Simulation Figure 2-13. Pre-layout simulation processMotherboard Layout and Routing Guidelines 2.5.1 Crosstalk and the Multi-Bit Adjustment Factor2.6 Validation 2.6.1 Flight Time MeasurementGuideline @ Processor Edge 2.6.2 Signal Quality MeasurementMotherboard Layout and Routing Guidelines Edge2.7 Timing Analysis Motherboard Layout and Routing GuidelinesThe terms used in the equations are described in Table Tflight,min Table 2-10. Recommended 100 MHz System Timing ParametersTable 2-11. Recommended 100 MHz System Flight Time Specs Motherboard Layout and Routing GuidelinesTable 2-12. Data and Associated Strobe 2.8.1 AGP Connector “Up Option Layout GuidelinesFigure 2-14. AGP Connector Layout Guidelines 2.8 AGP Layout and Routing GuidelinesMotherboard Layout and Routing Guidelines Table 2-14. Control Signal Line Length Recommendations2.8.2 On-board AGP Compliant Device “Down” Option Layout Guidelines Table 2-13. Source Synchronous Motherboard RecommendationsMotherboard Layout and Routing Guidelines Table 2-16. Control Signal Line Length RecommendationsFigure 2-15. On-board AGP Compliant Device Layout Guidelines Table 2-15. Source Synchronous Motherboard RecommendationsMotherboard Layout and Routing Guidelines Figure 2-16. FET Switch Example2.9 82443GX Memory Subsystem Layout and Routing Guidelines 2.9.1 100 MHz 82443GX Memory Array ConsiderationsTable 2-17. MDx lines Reference Planes Routing 2.9.1.1 Matching the Reference Planes2.9.1.2 Adding Additional Decoupling Capacitor Figure 2-17. Registered SDRAM DIMM ExampleMotherboard Layout and Routing Guidelines 2.9.2 Memory Layout & Routing Guidelines2.9.1.3 Trace Width vs. Trace Spacing Figure 2-19. 4 DIMMs Single or Double-SidedMotherboard Layout and Routing Guidelines Table 2-18. FET Switch DQ Route ExampleFigure 2-20. Motherboard Model-Data MDxx, 4 DIMMs 82443GXMotherboard Layout and Routing Guidelines Figure 2-21. Motherboard Model-DQMA0,24,67, 4 DIMMsFigure 2-22. Motherboard Model-DQMA1,5, 4 DIMMs Figure 2-23. Motherboard Model-DQMA1,5, 4 DIMMsMotherboard Layout and Routing Guidelines Figure 2-24. Motherboard Model-DQMB1,5, 4 DIMMsFigure 2-25. Motherboard Model-CSA#/CSB#, 4 DIMMs Figure 2-26. Motherboard Model-SRASA#, 4 DIMMsMotherboard Layout and Routing Guidelines Table 2-19. Motherboard Model SRASB#, 4 DIMMsTable 2-20. Motherboard Model SCASA#, 4 DIMMs Table 2-21. Motherboard Model SCASB#, 4 DIMMsMotherboard Layout and Routing Guidelines Table 2-22. Motherboard Model WEA#, 4 DIMMsTable 2-23. Motherboard Model WEB#, 4 DIMMs Table 2-24. Motherboard Model MAA140, 4 DIMMsFigure 2-27. Motherboard Model-Data MDxx Lines, 4 DIMMs No FET 2.9.3 4 DIMM Routing Guidelines NO FET2.9.4 PCI Bus Routing Guidelines Table 2-25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMsFigure 2-29. 82443GX Decoupling 2.9.5 Decoupling Guidelines Intel 440GX AGPset PlatformHost Bridge Controller 492 BGA Figure 2-28. PCI Bus Layout ExampleFigure 2-30. Clock Trace Spacing Guidelines 2.9.6 Intel 440GX AGPset Clock Layout Recommendations2.9.6.1 Clock Routing Spacing 2.9.6.2 System Bus Clock Layout2.9.6.3 PCI Clock Layout 2.9.6.4 SDRAM Clock LayoutMotherboard Layout and Routing Guidelines 2.9.6.5 AGP Clock Layout Figure 2-31. AGP Clock LayoutMotherboard Layout and Routing Guidelines Design Checklist Page 3.2 Pull-up and Pull-down Resistor Values Design ChecklistDesign Checklist 3.1 OverviewTable 3-1. Slot Connectivity Sheet 1 of 3.3 Intel Pentium II Processor Checklist3.3.1 Intel Pentium II Processor Figure 3-1. Pull-up Resistor ExampleTable 3-1. Slot Connectivity Sheet 2 of Design ChecklistIntel440GX AGPset Design Guide Intel440GX AGPset Design Guide Table 3-2. GND & Power Pin DefinitionTable 3-1. Slot Connectivity Sheet 3 of Design Checklist3.3.3 Intel Pentium II Processor Signals 3.3.2 Intel Pentium II Processor ClocksDesign Checklist DBRESET ITP Reset signal requires a 240 ohm pull-up to VCC3 Design Checklist3.3.7 Voltage Regulator Module, VRM 3.3.4 Uni-Processor UP Slot 1 Checklist3.3.5 Dual-Processor DP Slot 1 Checklist 3.3.6 Slot 1 Decoupling CapacitorsDesign Checklist 3.4 Intel 440GX AGPset Clocks3.4.1 CK100 - 100 MHz Clock Synthesizer Table 3-3. Processor Frequency SelectDesign Checklist 3.4.2 CKBF - SDRAM 1 to 18 Clock Buffer3.4.3 GCKE and DCLKWR Connection Figure 3-2. GCKE & DCLKWR ConnectionsDesign Checklist 3.5 82443GX Host Bridge3.5.1 82443GX Interface Table 3-4. 82443GX Connectivity Sheet 1 of3-11 Table 3-4. 82443GX Connectivity Sheet 2 ofDesign Checklist Intel440GX AGPset Design GuideDesign Checklist 3.5.2 82443GX GTL+ Bus Interface3.5.3 82443GX PCI Interface Table 3-4. 82443GX Connectivity Sheet 3 of3.5.4 82443GX AGP Interface Table 3-5. Strapping OptionsDesign Checklist Design Checklist 3.6 Intel 440GX AGPset Memory Interface3.6.1 SDRAM Connections Table 3-6. SDRAM ConnectivityDesign Checklist 3.6.2 DIMM Solution With FET SwitchesFigure 3-3. Current Solution With Existing FET Switches 3.6.3 Registered SDRAMDesign Checklist 3.7 82371EB PIIX4E3.7.1 PIIX4E Connections Table 3-7. PIIX4E Connectivity Sheet 1 of3-17 Table 3-7. PIIX4E Connectivity Sheet 2 ofDesign Checklist Intel440GX AGPset Design Guide3-18 Table 3-7. PIIX4E Connectivity Sheet 3 ofDesign Checklist Intel440GX AGPset Design Guide3-19 Table 3-7. PIIX4E Connectivity Sheet 4 ofDesign Checklist Intel440GX AGPset Design GuideTable 3-8. IDE Series Termination 3.7.2 IDE Routing Guidelines3.7.2.1 Cabling 3.7.2.2 MotherboardFigure 3-4. Series Resistor Placement for Primary IDE Connectors PIIX4EDesign Checklist Design Checklist 3.8 PCI Bus Signals3.7.3 PIIX4E Power And Ground Pins Table 3-9. PIIX4E PWR & GNDTable 3-11. Non-PIIX4E ISA Signals ISA Signals3.10 ISA and X-Bus Signals Table 3-10. Non-PIIX4E PCI SignalsDesign Checklist 3.11 USB Interface3.12 IDE Interface Table 3-12. Non-PIIX4E IDEFigure 3-5. Dual Footprint Flash Layouts 3.13 Flash Design3.13.1 Dual-Footprint Flash Design 3.13.2 Flash Design ConsiderationsFigure 3-6. nterfacing Intel’s Flash with PIIX4E in Desktop XD701Mbit/2Mbit FlashTable 3-13. Flash Vpp Recommendations Design ChecklistWrite Protection Design Checklist 3.14 System and Test Signals3.15 Power Management Signals Figure 3-7. Interfacing Intel’s Flash with PIIX4E in DesktopNote The polarities have been altered to simplify drawing Simplified P W R G O O D a n d P W R O K generation logic VCC3A S L O T O C C B S L O T O C C4.7K V R M 1 P W R G D V R M 2 P W R G D I T P R E S E T A T X P S P O KDesign Checklist 3.15.1 Power Button ImplementationDesign Checklist 3.16 MiscellaneousDesign Checklist 3.17 82093AA IOAPICDesign Checklist 3.18.1 Max1617 Temperature Sensor3.18 Manageability Devices 3.18.2 LM79 Microprocessor System Hardware MonitorDesign Checklist 3.18.3 82558B LOM ChecklistDesign Checklist 3.19 Software/BIOS3.19.1 USB and Multi-processor BIOS 3.18.4 Wake On LAN WOL Header3.20.1 Design Considerations 3.20 Thermals / Cooling Solutions3.21 Mechanicals 3.19.2 Design ConsiderationsDesign Checklist 3.22 Electricals3.21.1 Design Considerations 3.22.1 Design Considerations3.23.2 Design Consideration 3.23 Layout Checklist3.24 Applications and Add-in Hardware 3.23.1 Routing and Board FabricationDebug Recommendations Page 4.2.1 Logic Analyzer Interface LAI Debug Recommendations4.1 Slot 1 Test Tools 4.2 Debug/Simulation Tools4.2.4 I/O Buffer Models 4.3 Debug Features4.3.1 Intel Pentium II Processor LAI Issue 4.2.3 Bus Functional Model BFMDebug Recommendations Figure 4-1. LAI Probe Input CircuitDebug Recommendations 4.3.2 Debug Logic Recommendations4.3.3.1 Design Considerations 4.3.4 Debug Procedures4.3.3 Debug Layout 4.3.2.1 Debug ConsiderationsDM = 0, D3-D0 = 1111 all including self shorthand Debug RecommendationsThird Party Vendors Page Third-Party Vendor Information Table 5-1. Slot 1 ConnectorThird-Party Vendor Information ProcessorsTable 5-5. Voltage Regulator Control Silicon Vendors 5.1.1 Voltage Regulator Modules5.1.2 Voltage Regulator Control Silicon Table 5-4. Voltage Regulator ModulesTable 5-8. FET Switch Vendors 5.2.2 Power Management Components5.2.3 FET Switches4 DIMM/FET Design Table 5-7. Power Management Component Vendors5.3.3 Heat sinks 5.3.1 Slot 1 Connector5.3 Other Processor Components 5.3.2 Mechanical SupportReference Design Schematics Page 4 and Intel 440GX AGPset Platform ReferenceDesign Intel440GX AGPset Platform Reference DesignThe GCKE shift register circuit is also shown Intel440GX AGPset Platform Reference DesignUltra I/O Component Intel440GX AGPset Platform Reference Design34-35 Power Connectors Front Panel JumpersIntel440GX AGPset Platform Reference Design Pull-up and Pull-down Resistors