Intel 440GX Simplified P W R G O O D a n d P W R O K generation logic VCC3, Design Checklist

Design Checklist

standby voltage is not provided by the power supply, then tie PWROK signal on the PIIX4E to the RSMRST# signal.

•If an 8.2K ohm resistor divider is used to divide the RSMRST# signal down to a 3V level for input to the PIIX4E, the rise time of this signal will be approximately 170ns (based on the input capacitance of the PIIX4E), which is within the maximum 250ns requirement of the PIIX4E. It is important that if any other components are connected to RSMRST#, the resistor divider values may need to be adjusted to meet a faster rise time required by the other devices and increased loading. 3V driving devices, such as an 74LVC14 could also be used as a replacement for the voltage divider.

•It is important to prevent glitches on the PWROK signal while the core well is being powered up or down. To accommodate this, the reference schematics shows a pull-up resistor to 3VSB in the last stage of this circuitry to keep PWROK from glitching when the core supply goes out of regulation.

•All logic and pull-ups in the path of PWRGOOD to the CPU, and PWROK to the PIIX4E (with the above exception) can be powered from the core supply.

•The PWROK signal to the chipset is a 3V signal.

•The core well power valid to PWROK asserted at the chipset is a minimum of 1msec.

•PWROK to the chipset must be deasserted a minimum of 0ns after RSMRST#.

•PWRGOOD signal to CPU is driven with an open collector buffer pulled up to 2.5V using a 330 ohm resistor.

•Below is a simplified diagram of the PWRGOOD and PWROK logic which is connected to the CPU slots and PIIX4E respectively in a DP system. The circuitry checks for both slots occupied, both CPU VRMs powered up, and the PS_POK signal from the ATX power supply connector before asserting PWRGOOD and PWROK to the CPU and PIIX4E. A reset button override pull-down is also included, causing the PWRGOOD and PWROK signals to get deasserted when pressed.

Figure 3-8. PWRGOOD & PWROK Logic

Simplified

P W R G O O D a n d P W R O K

generation logic

VCC3

A _ S L O T O C C

B _ S L O T O C C4.7K V R M 1 _ P W R G D

V R M 2 _ P W R G D

I T P _ R E S E T

A T X _ P S _ P O K

Note: The polarities have been altered to simplify drawing.

PWRGOOD to CPU

(2.5V)

PWROK to PIIX4E (3.3V)

v 0 1 1

•The following should be considered when implementing a RESET BUTTON for desktop based systems:

Intel®440GX AGPset Design Guide 3-29