Design Checklist

—TMS (connector pin A3) and TDI (connector pin A4) should be independently bussed and pulled up with 5K ohm (approximate) resistors.

—TRST# (connector pin A1) and TCK (connector pin B2) should be independently bussed and pulled down with 5K ohm (approximate) resistors.

—TDO (connector pin B4) should be left open.

3.5.482443GX AGP Interface

•The following will help reduce the AGPREF margin needed when data is being written or read via the AGP bus interface.

—Use only two 1% resistors for the AGPREF voltage divider on the 82443GX boards. This will limit the AGPREF margin needed to 100mV below 40% of Vcc. If 5% resistors are used, the AGPREF margin needed would be 160mV.

—Have “at least” 2x spacing around Strobe A and B to decrease crosstalk inductive coupling from adjacent GAD signals. This could reduce crosstalk by as much as 100-300 mV.

•The AGP interface is designed for a 3.3V operating environment, and both the master and target AGP compliant devices must be driven by the same supply line.

•No external termination for signal quality is required by the AGP spec., but can be added to improve signal integrity provided the timing constraints are still satisfied.

•AGP interrupts may be shared with PCI interrupts similar to the recommendations in the PCI 2.1 spec. For example, in a system with 3 PCI slots and one AGP slot, interrupts should be connected such that each of the four INTA# lines hooks to a unique input on the PIIX4E. It is recommended that the interrupts be staggered. It is also recommended that each PIRQ be programmed to a different IRQ if possible.

•It is the requirement of the motherboard designer to properly interface the AGP interrupts to the PCI bus. In this reference design, the AGP interrupts are pulled up to 3.3V, and a buffer is used to isolate the 5V environment from the AGP bus.

•To minimize the impact of any mismatch between the motherboard and the add-in card, a board impedance of 65 ±15 ohms is strongly recommended.

•At each component that requires it, AGP_Vref should be generated locally from the AGP interface Vddq rail.

Table 3-5. Strapping Options

Signal

Description

Register

Pulled to ‘0’

Pulled to ‘1’

 

 

 

 

 

MAB9#

AGP Signals

PMCR[1]

AGP Enabled (Default)

AGP Disabled

 

 

 

 

 

MAB11#

In Order Queue

MGXCFG[2]

Non-Pipelined

Maximum Queue Depth

Depth

Enabled (Default)

 

 

 

 

 

 

 

 

MAB12#

Host Frequency

NGXCFG[13]

Reserved

100MHz (Default)

 

 

 

 

 

NOTES:

1.MAB[9]# is connected to internal 50K ohm pull-down resistors. MAB[12:11] are connected to internal 50K ohm pull-up resistors.

2.Note that strapping signals are not driven by the 82443GX during reset sequence. Proper strapping must be used to define logical values for these signals. Default values provided by the internal pull-up or pull-down resistors can be overridden by an external resistor.

3.When AGP is disabled, all AGP signals are tri-stated and isolated. They do not need external pull-up resistors. The AGP signals are PIPE#, SBA[7:0], RBF#, ST[2:0], GADSTBA, GADSTBB, SBSTB, GFRAME#, GIRDY#, GTRDY#, GSTOP#, GDEVSEL#, GREQ#, GGNT#, GAD[31:0], FC/BE[3:0]#, GPAR.

4.When AGP is disabled, tie AGP_Vref to ground.

Intel®440GX AGPset Design Guide

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Intel 440GX manual 4 82443GX AGP Interface, Strapping Options, Signal Description Register Pulled to ‘0’ Pulled to ‘1’
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440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
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