PCI Bus Signals, PIIX4E Power And Ground Pins

Design Checklist

3.7.3PIIX4E Power And Ground Pins

•Vcc, Vcc(RTC), Vcc(SUS), and Vcc(USB) must be tied to 3.3V.

•VREF must be tied to 5V in a 5V tolerant system. This signal must be power up before or simultaneous to Vcc, and it must be power down after or simultaneous to Vcc. For the layout

guidelines, refer to the Pin Description section of the PIIX4E datasheet. The VREF circuitry can be shared between 82443GX and the PIIX4E. If the circuitry is placed close to the PIIX4E, then ensure that an extra 1uF capacitor is placed on the VREF pin of the 82443GX.

— STR support: For systems implementing STR support, a separate V REF circuit must be used for each of the two devices since the PIIX4E Core and the 82443GX Host Bridge should be supplied by the different power planes.

— No STR support: The V REF circuitry can be shared between 82443GX and the PIIX4E. If the circuitry is placed close to the PIIX4E, then ensure that an extra 1uF capacitor is placed on the VREF pin of the 82443GX.

•Use a Schottky diode in the VREF circuit for a minimum voltage drop from VCC3.3 to VREF because there is an internal diode in parallel to the Schottky diode that does not have high current capability. The Schottky diode will begin to conduct first, therefore carrying the high current.

•VREF can be tied to Vcc in a non-5V tolerant system.

•Tie Vss and Vss(USB) to ground.

Table 3-9. PIIX4E PWR & GND

	VCC		VCC(RTC)	VCC(SUS)	VCC(USB)	VSS(USB)		VSS

E9		F15	L16	N16	K5	J5	D10		L9-L12

E11		G6		R16			E7		M9-M12

E12		P15					E13

E16		R6					J9-J12

F5		R7					K9-K12

F6		R15

F14		T6

3.8PCI Bus Signals

A specific board sensitivity has been identified that may result in a low going glitch on a deasserted PCIRST# signal when it is lightly loaded. This glitch may occur as a result of VCC droop caused by simultaneous switching of most/all AD[31:0] signals from 0 to 1. This glitch can in some designs be low enough (below 1.7V) to interfere with proper operation of the Host PCI Bridge Controller component.

This sensitivity manifests itself on designs where PCIRST# is lightly loaded with less than approximately 50pF, or is not driving the entire PCI bus. Design features that could aggravate the problem are; an in-line active component on the PCIRST# signal, such as an AND gate or, lack of a series termination resistor on the PCIRST# signal at the PIIX4 or PIIX4E.

There are several improvements that can be implemented individually or in any combination. First, a series termination resistor between 22 and 33 ohms placed close to the PIIX4/PIIX4E will help reduce the glitch. Second, an external capacitor of approximately 47pF will help reduce the glitch.

Intel®440GX AGPset Design Guide

3-22

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.

Intel 440GX manual PCI Bus Signals, PIIX4E Power And Ground Pins, PIIX4E PWR & GND

Models: 440GX