Intel 440GX AGPset
Design Guide
March
Intel440GX AGPset Design Guide
Contents
Validation
82371EB PIIX4E
4.3.1 IntelPentiumII Processor LAI Issue
Figures
Tables
Revision History
Intel440GX AGPset Design Guide
Date
Revision
Intel440GX AGPset Design Guide
Introduction
Page
1.1 About This Design Guide
Introduction
Introduction
1.2 References
Intel 440GX AGPset Datasheet WWW order number
Introduction
AP-589 EMI WWW order number
1.3.1 Intel Pentium II Processor
1.3 Intel Pentium II Processor / Intel 440GX AGPset Overview
Introduction
1.3.2 Intel 440GX AGPset
Introduction
1.3.2.1 System Bus Interface
1.3.2.2 DRAM Interface
1.3.2.3 Accelerated Graphics Port Interface
Introduction
1.3.4 Wired for Management Initiative
1.3.3 PCI-to-ISA/IDE Xcelerator PIIX4E
1.3.2.4 PCI Interface
1.3.2.5 System Clocking
1.3.3.1 Instrumentation
1.3.3.2 Remote Service Boot
Introduction
1.3.3.4 Power Management
1.4 Design Recommendations
1.4.1 Voltage Definitions
1.3.3.3 Remote Wake-Up
1.4.2 General Design Recommendations
1.4.3 Transitioning from Intel 440BX AGPset to Intel 440GX
AGPset Design
Introduction
Introduction
Intel440GX AGPset Design Guide
Motherboard Design
Page
Figure 2-1. Major Signal Sections 82443GX Top View
Motherboard Layout and Routing
Guidelines
2.1 BGA Quadrant Assignment
Motherboard Layout and Routing Guidelines
ATX Form Factor
Motherboard Layout and Routing Guidelines
2.2 Board Description
NLX Form Factor
Figure 2-4. Four Layer Board Stack-up
Motherboard Layout and Routing Guidelines
2.3 Routing Guidelines
Motherboard Layout and Routing Guidelines
2.3.1 GTL+ Description
2.3.2 GTL+ Layout Recommendations
2.3.3 Single Processor Design
2.3.3.1 Single Processor Network Topology and Conditions
Table 2-1. Recommended Trace Lengths for Single Processor Design
2.3.3.2 Single Processor Recommended Trace Lengths
Motherboard Layout and Routing Guidelines
2.3.4 Dual Processor Systems
2.3.5 Single Processor Systems-Single-End Termination SET
2.3.4.1 Dual Processor Network Topology and Conditions
2.3.4.2 Dual Processor Recommended Trace Lengths
Table 2-3. SET Trace Length Requirements
2.3.5.2 SET Trace Length Requirements
Motherboard Layout and Routing Guidelines
2.3.6 Additional Guidelines
2.3.6.1 Minimizing Crosstalk
2.3.6.2 Practical Considerations
Motherboard Layout and Routing Guidelines
2.3.7 Design Methodology
Motherboard Layout and Routing Guidelines
Figure 2-12. GTL+ Design Process
2.3.8 Performance Requirements
Motherboard Layout and Routing Guidelines
2.3.9 Topology Definition
2.3.10 Pre-Layout Simulation Sensitivity Analysis
2.3.11 Simulation Methodology
Table 2-4. Recommended 100 MHz System Flight Time Specs
2.4 Placement & Layout
2.5 Post-Layout Simulation
Figure 2-13. Pre-layout simulation process
Motherboard Layout and Routing Guidelines
2.5.1 Crosstalk and the Multi-Bit Adjustment Factor
2.6 Validation
2.6.1 Flight Time Measurement
Motherboard Layout and Routing Guidelines
2.6.2 Signal Quality Measurement
Motherboard Layout and Routing Guidelines
Edge
Guideline @ Processor Edge
Motherboard Layout and Routing Guidelines
2.7 Timing Analysis
The terms used in the equations are described in Table
Table 2-10. Recommended 100 MHz System Timing Parameters
Table 2-11. Recommended 100 MHz System Flight Time Specs
Motherboard Layout and Routing Guidelines
Tflight,min
2.8.1 AGP Connector “Up Option Layout Guidelines
Figure 2-14. AGP Connector Layout Guidelines
2.8 AGP Layout and Routing Guidelines
Table 2-12. Data and Associated Strobe
Table 2-14. Control Signal Line Length Recommendations
2.8.2 On-board AGP Compliant Device “Down” Option Layout Guidelines
Table 2-13. Source Synchronous Motherboard Recommendations
Motherboard Layout and Routing Guidelines
Table 2-16. Control Signal Line Length Recommendations
Figure 2-15. On-board AGP Compliant Device Layout Guidelines
Table 2-15. Source Synchronous Motherboard Recommendations
Motherboard Layout and Routing Guidelines
Figure 2-16. FET Switch Example
2.9 82443GX Memory Subsystem Layout and Routing Guidelines
2.9.1 100 MHz 82443GX Memory Array Considerations
Motherboard Layout and Routing Guidelines
2.9.1.1 Matching the Reference Planes
2.9.1.2 Adding Additional Decoupling Capacitor
Figure 2-17. Registered SDRAM DIMM Example
Table 2-17. MDx lines Reference Planes Routing
2.9.2 Memory Layout & Routing Guidelines
2.9.1.3 Trace Width vs. Trace Spacing
Figure 2-19. 4 DIMMs Single or Double-Sided
Motherboard Layout and Routing Guidelines
Table 2-18. FET Switch DQ Route Example
Figure 2-20. Motherboard Model-Data MDxx, 4 DIMMs
82443GX
Motherboard Layout and Routing Guidelines
Figure 2-21. Motherboard Model-DQMA0,24,67, 4 DIMMs
Figure 2-22. Motherboard Model-DQMA1,5, 4 DIMMs
Figure 2-23. Motherboard Model-DQMA1,5, 4 DIMMs
Motherboard Layout and Routing Guidelines
Figure 2-24. Motherboard Model-DQMB1,5, 4 DIMMs
Figure 2-25. Motherboard Model-CSA#/CSB#, 4 DIMMs
Figure 2-26. Motherboard Model-SRASA#, 4 DIMMs
Motherboard Layout and Routing Guidelines
Table 2-19. Motherboard Model SRASB#, 4 DIMMs
Table 2-20. Motherboard Model SCASA#, 4 DIMMs
Table 2-21. Motherboard Model SCASB#, 4 DIMMs
Motherboard Layout and Routing Guidelines
Table 2-22. Motherboard Model WEA#, 4 DIMMs
Table 2-23. Motherboard Model WEB#, 4 DIMMs
Table 2-24. Motherboard Model MAA140, 4 DIMMs
Motherboard Layout and Routing Guidelines
2.9.3 4 DIMM Routing Guidelines NO FET
2.9.4 PCI Bus Routing Guidelines
Table 2-25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs
Figure 2-27. Motherboard Model-Data MDxx Lines, 4 DIMMs No FET
2.9.5 Decoupling Guidelines Intel 440GX AGPset Platform
Host Bridge Controller 492 BGA
Figure 2-28. PCI Bus Layout Example
Figure 2-29. 82443GX Decoupling
2.9.6 Intel 440GX AGPset Clock Layout Recommendations
2.9.6.1 Clock Routing Spacing
2.9.6.2 System Bus Clock Layout
Figure 2-30. Clock Trace Spacing Guidelines
2.9.6.4 SDRAM Clock Layout
2.9.6.3 PCI Clock Layout
Motherboard Layout and Routing Guidelines
Figure 2-31. AGP Clock Layout
2.9.6.5 AGP Clock Layout
Motherboard Layout and Routing Guidelines
Design Checklist
Page
Design Checklist
Design Checklist
3.1 Overview
3.2 Pull-up and Pull-down Resistor Values
3.3 Intel Pentium II Processor Checklist
3.3.1 Intel Pentium II Processor
Figure 3-1. Pull-up Resistor Example
Table 3-1. Slot Connectivity Sheet 1 of
Design Checklist
Table 3-1. Slot Connectivity Sheet 2 of
Intel440GX AGPset Design Guide
Table 3-2. GND & Power Pin Definition
Table 3-1. Slot Connectivity Sheet 3 of
Design Checklist
Intel440GX AGPset Design Guide
3.3.2 Intel Pentium II Processor Clocks
3.3.3 Intel Pentium II Processor Signals
Design Checklist
Design Checklist
DBRESET ITP Reset signal requires a 240 ohm pull-up to VCC3
3.3.4 Uni-Processor UP Slot 1 Checklist
3.3.5 Dual-Processor DP Slot 1 Checklist
3.3.6 Slot 1 Decoupling Capacitors
3.3.7 Voltage Regulator Module, VRM
3.4 Intel 440GX AGPset Clocks
3.4.1 CK100 - 100 MHz Clock Synthesizer
Table 3-3. Processor Frequency Select
Design Checklist
3.4.2 CKBF - SDRAM 1 to 18 Clock Buffer
3.4.3 GCKE and DCLKWR Connection
Figure 3-2. GCKE & DCLKWR Connections
Design Checklist
3.5 82443GX Host Bridge
3.5.1 82443GX Interface
Table 3-4. 82443GX Connectivity Sheet 1 of
Design Checklist
Table 3-4. 82443GX Connectivity Sheet 2 of
Design Checklist
Intel440GX AGPset Design Guide
3-11
3.5.2 82443GX GTL+ Bus Interface
3.5.3 82443GX PCI Interface
Table 3-4. 82443GX Connectivity Sheet 3 of
Design Checklist
Table 3-5. Strapping Options
3.5.4 82443GX AGP Interface
Design Checklist
3.6 Intel 440GX AGPset Memory Interface
3.6.1 SDRAM Connections
Table 3-6. SDRAM Connectivity
Design Checklist
3.6.2 DIMM Solution With FET Switches
Figure 3-3. Current Solution With Existing FET Switches
3.6.3 Registered SDRAM
Design Checklist
3.7 82371EB PIIX4E
3.7.1 PIIX4E Connections
Table 3-7. PIIX4E Connectivity Sheet 1 of
Design Checklist
Table 3-7. PIIX4E Connectivity Sheet 2 of
Design Checklist
Intel440GX AGPset Design Guide
3-17
Table 3-7. PIIX4E Connectivity Sheet 3 of
Design Checklist
Intel440GX AGPset Design Guide
3-18
Table 3-7. PIIX4E Connectivity Sheet 4 of
Design Checklist
Intel440GX AGPset Design Guide
3-19
3.7.2 IDE Routing Guidelines
3.7.2.1 Cabling
3.7.2.2 Motherboard
Table 3-8. IDE Series Termination
PIIX4E
Figure 3-4. Series Resistor Placement for Primary IDE Connectors
Design Checklist
3.8 PCI Bus Signals
3.7.3 PIIX4E Power And Ground Pins
Table 3-9. PIIX4E PWR & GND
Design Checklist
ISA Signals
3.10 ISA and X-Bus Signals
Table 3-10. Non-PIIX4E PCI Signals
Table 3-11. Non-PIIX4E ISA Signals
3.11 USB Interface
3.12 IDE Interface
Table 3-12. Non-PIIX4E IDE
Design Checklist
3.13 Flash Design
3.13.1 Dual-Footprint Flash Design
3.13.2 Flash Design Considerations
Figure 3-5. Dual Footprint Flash Layouts
XD70
1Mbit/2Mbit
Flash
Figure 3-6. nterfacing Intel’s Flash with PIIX4E in Desktop
Design Checklist
Table 3-13. Flash Vpp Recommendations
Write Protection
3.14 System and Test Signals
3.15 Power Management Signals
Figure 3-7. Interfacing Intel’s Flash with PIIX4E in Desktop
Design Checklist
Simplified P W R G O O D a n d P W R O K generation logic VCC3
A S L O T O C C B S L O T O C C4.7K V R M 1 P W R G D
V R M 2 P W R G D I T P R E S E T A T X P S P O K
Note The polarities have been altered to simplify drawing
3.15.1 Power Button Implementation
Design Checklist
3.16 Miscellaneous
Design Checklist
3.17 82093AA IOAPIC
Design Checklist
3.18.1 Max1617 Temperature Sensor
3.18 Manageability Devices
3.18.2 LM79 Microprocessor System Hardware Monitor
Design Checklist
3.18.3 82558B LOM Checklist
Design Checklist
3.19 Software/BIOS
3.19.1 USB and Multi-processor BIOS
3.18.4 Wake On LAN WOL Header
Design Checklist
3.20 Thermals / Cooling Solutions
3.21 Mechanicals
3.19.2 Design Considerations
3.20.1 Design Considerations
3.22 Electricals
3.21.1 Design Considerations
3.22.1 Design Considerations
Design Checklist
3.23 Layout Checklist
3.24 Applications and Add-in Hardware
3.23.1 Routing and Board Fabrication
3.23.2 Design Consideration
Debug Recommendations
Page
Debug Recommendations
4.1 Slot 1 Test Tools
4.2 Debug/Simulation Tools
4.2.1 Logic Analyzer Interface LAI
4.3 Debug Features
4.3.1 Intel Pentium II Processor LAI Issue
4.2.3 Bus Functional Model BFM
4.2.4 I/O Buffer Models
Figure 4-1. LAI Probe Input Circuit
Debug Recommendations
4.3.2 Debug Logic Recommendations
Debug Recommendations
4.3.4 Debug Procedures
4.3.3 Debug Layout
4.3.2.1 Debug Considerations
4.3.3.1 Design Considerations
Debug Recommendations
DM = 0, D3-D0 = 1111 all including self shorthand
Third Party Vendors
Page
Table 5-1. Slot 1 Connector
Third-Party Vendor Information
Processors
Third-Party Vendor Information
5.1.1 Voltage Regulator Modules
5.1.2 Voltage Regulator Control Silicon
Table 5-4. Voltage Regulator Modules
Table 5-5. Voltage Regulator Control Silicon Vendors
5.2.2 Power Management Components
5.2.3 FET Switches4 DIMM/FET Design
Table 5-7. Power Management Component Vendors
Table 5-8. FET Switch Vendors
5.3.1 Slot 1 Connector
5.3 Other Processor Components
5.3.2 Mechanical Support
5.3.3 Heat sinks
Reference Design Schematics
Page
Intel 440GX AGPset Platform Reference
Design
Intel440GX AGPset Platform Reference Design
4 and
Intel440GX AGPset Platform Reference Design
The GCKE shift register circuit is also shown
Intel440GX AGPset Platform Reference Design
Ultra I/O Component
Power Connectors Front Panel Jumpers
Intel440GX AGPset Platform Reference Design
Pull-up and Pull-down Resistors
34-35
