Texas Instruments TMS320DM644x instruction

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Peripheral Architecture

Figure 2. MMC/SD Controller Interface Diagram

MMCs or SD cards

ARM
MMC/SD
controller	Native
CMD	signals
CMD
	Native packets
DAT0 or DAT0−3
CLK
Memory
EDMA

Figure 3. MMC Configuration and SD Configuration Diagram

MMC/SD configuration

MMC/SD controller

MMC and SD (1−bit mode)

SD_CLK CLK

SD_CMD CMD

SD_DATA0 DAT0

SD_DATA1

SD_DATA2

SD_DATA3

SD configuration

MMC/SD controller

SD card (4−bit mode)

SD_CLK CLK

SD_CMD CMD

SD_DATA0 DAT0

SD_DATA1 DAT1

SD_DATA2 DAT2

SD_DATA3 DAT3

SPRUE30B –September 2006

Multimedia Card (MMC)/Secure Digital (SD) Card Controller

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Texas Instruments TMS320DM644x manual MMC/SD Controller Interface Diagram

Contents

Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Supported Use Case Statement MMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking Diagram Protocol Descriptions Signal DescriptionsMMC/SD Controller Pins Used in Each Mode 1 MMC/SD Mode Write Sequence Portion Sequence Description MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence RD CMD MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo CRC Fifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Support byten = 1111 1110 CPU Reads Fifo Operation During Card Read OperationEdma Reads Fifo Operation During Card Read Diagram CPU Writes Fifo Operation During Card Write OperationEdma Writes Fifo Operation During Card Write Diagram Initialization Reset Considerations Initialize the Data Block Registers Mmcblen and Mmcnblk Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Time-Out Registers Mmctor and Mmctod Determining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD Mode Checking For a Data Transmit Empty Condition Description of MMC/SD Interrupt Requests Interrupt SupportInterrupt Events and Requests Interrupt Multiplexing Emulation Considerations Power ManagementDMA Event Support Card Identification Operation MMC Card Identification Procedure Procedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using Edma Offset Acronym Register Description Bit Field Value Description MMC Control Register MmcctlMMC Control Register Mmcctl Field Descriptions Clken MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions Clken Clkrt Bit Field MMC Status Register 0 MMCST0MMC Status Register 0 MMCST0 Field Descriptions Write-data CRC error Fifoful MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy Etrndne MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions Etrndne Edated Edrrdy Edxrdy TOR MMC Response Time-Out Register MmctorMMC Response Time-Out Register Mmctor Field Descriptions MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register Mmctod Blen MMC Block Length Register MmcblenMMC Block Length Register Mmcblen Field Descriptions Nblk MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register Mmcnblk Field Descriptions MMC Data Transmit Register Mmcdxr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Receive Register Mmcdrr Field Descriptions Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions Dmatrig CRC7 Stream enableBit Position Command Register Description Argl MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions Argh MMC Response Registers MMCRSP0-MMCRSP7 MMCRSP4-0 R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits Bit Position of Response Register MMC Data Response Register Mmcdrsp Field Descriptions MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register Mmcdrsp Accwd MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions Accwd Fifolev Fifodir Fiforst Reference Additions/Modifications/Deletions Table A-1. Document Revision History Appendix a Important Notice