Procedures for Common Operations | Texas Instruments TMS320DM644x

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Procedures for Common Operations

Figure 12. MMC Card Identification Procedure

3.1.2SD Card Identification Procedure

The SD card identification procedure is:

1.Use the MMC command register (MMCCMD) to issue the GO_IDLE_STATE (CMD0) command to the MMC cards. Using MMCMD to issue the CMD0 command puts all cards (MMC and SD) in the idle state and no response from the cards is expected.

2.Use MMCCMD to issue the APP_CMD (CMD55) command (R1 response is expected) to indicate that the command that follows is an application command.

3.Use MMCCMD to send the SD_SEND_OP_COND (ACMD41) command with the voltage range supported (R3 response is expected) to SD cards. Using MMCCMD to send the ACMD41 command allows the host to identify and reject cards that do not match the VDD range that the host supports.

4.Use MMCCMD to send the ALL_SEND_CID (CMD2) command (R2 response is expected) to the MMC cards. Using MMCCMD to send the CMD2 command notifies all cards to send their unique card identification (CID) number. There should only be one card that successfully sends its full CID number to the host. The successful card goes into identification state and does not respond to this command again.

5.Use MMCMD to issue the SEND_RELATIVE_ADDR (CMD3) command (R1 response is expected) in order to ask the card to publish a new relative address for future use to address the card in data transfer mode.

Note: This command is only addressed to the card that successfully sent its CID number in step 4. This card now goes into standby mode. This card also changes its output drivers from open-drain to push-pull. It stops replying to the CMD2 command, allowing for the identification of other cards.

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Multimedia Card (MMC)/Secure Digital (SD) Card Controller

SPRUE30B –September 2006

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Texas Instruments TMS320DM644x manual Procedures for Common Operations

Contents

Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Features Functional Block DiagramPurpose of the Peripheral Supported Use Case Statement Industry Standards Compliance Statement MMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock Control 1 MMC/SD Mode Write Sequence Signal DescriptionsMMC/SD Controller Pins Used in Each Mode Protocol Descriptions MMC/SD Mode Write Sequence 2 MMC/SD Mode Read SequencePortion Sequence Description CRC MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo RD CMD Fifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = 1st 2nd 3rd 4th Support byten = 1111 1110 Fifo Operation During Card Read Operation Edma ReadsCPU Reads Fifo Operation During Card Read Diagram Fifo Operation During Card Write Operation Edma WritesCPU Writes Fifo Operation During Card Write Diagram Reset Considerations Initialization Initialize the Time-Out Registers Mmctor and Mmctod Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Data Block Registers Mmcblen and Mmcnblk Monitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in Mmcdrr Checking For a Data Transmit Empty Condition Interrupt Multiplexing Interrupt SupportInterrupt Events and Requests Description of MMC/SD Interrupt Requests Power Management DMA Event SupportEmulation Considerations MMC Card Identification Procedure Card Identification Operation Procedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read Operation MMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Offset Acronym Register Description MMC Control Register Mmcctl MMC Control Register Mmcctl Field DescriptionsBit Field Value Description Clken Clkrt MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions Clken MMC Status Register 0 MMCST0 MMC Status Register 0 MMCST0 Field DescriptionsBit Field Write-data CRC error Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions Fifoful Etrndne Edated Edrrdy Edxrdy MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions Etrndne MMC Response Time-Out Register Mmctor MMC Response Time-Out Register Mmctor Field DescriptionsTOR MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Block Length Register Mmcblen MMC Block Length Register Mmcblen Field DescriptionsBlen MMC Number of Blocks Register Mmcnblk Field Descriptions MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc Nblk MMC Data Receive Register Mmcdrr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Transmit Register Mmcdxr Field Descriptions Dmatrig MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen Stream enable Bit Position Command Register DescriptionCRC7 Argh MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions Argl MMC Response Registers MMCRSP0-MMCRSP7 Bit Position of Response Register R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits MMCRSP4-0 MMC Data Response Register Mmcdrsp MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register Mmcdrsp Field Descriptions Accwd Fifolev Fifodir Fiforst MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions Accwd Table A-1. Document Revision History Reference Additions/Modifications/Deletions Appendix a Important Notice