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Procedures for Common Operations
3.3MMC/SD Mode Single-Block Write Operation Using the EDMA
To perform a
The procedure for this operation is as follows:
1.Write the card’s relative address to the MMC argument registers (MMCARGH and MMCARGL). Load the high part of the address to MMCARGH and the low part of the address to MMCARGL.
2.Read the card CSD to determine the card'smaximum block length.
3.Use the MMC command register (MMCCMD) to send the SET_BLOCKLEN command (if the block length is different than the length used in the previous operation). The block length must be a multiple of 512 bytes and less then the maximum block length specified in the CSD.
4.Reset the FIFO (FIFORST bit in MMCFIFOCTL).
5.Set the FIFO direction to transmit (FIFODIR bit in MMCFIFOCTL).
6.Set the access width (ACCWD bits in MMCFIFOCTL).
7.Set the FIFO threshold (FIFOLEV bit in MMCFIFOCTL).
8.Set up the DMA (DMA size must be greater than or equal to the FIFOLEV setting).
9.Use MMCCMD to send the WRITE _BLOCK command to the card (set the DMATRIG bit in MMCCMD to trigger the first DMA).
10.Wait for the DMA sequence to complete or for the DATADNE flag in the MMC status register 0 (MMCST0) to be set.
11.Use MMCST0 to check for errors.
3.4MMC/SD Mode Single-Block Read Operation Using the CPU
To perform a
The procedure for this operation is as follows:
1.Write the card’s relative address to the MMC argument registers (MMCARGH and MMCARGL). Load the high part of the address to MCARGH and the low part of the address to MMCARGL.
2.Use the MMC command register (MMCCMD) to send the SELECT/DESELECT_CARD broadcast command. This selects the addressed card and deselects the others.
3.Write the source start address to the MMC argument registers. Load the high part to MMCARGH and the low part to MMCARGL.
4.Read card CSD to determine the card'smaximum block length.
5.Use MMCCMD to send the SET_BLOCKLEN command (if the block length is different than the length used in the previous operation). The block length must be a multiple of 512 bytes and less then the maximum block length specified in the CSD.
6.Reset the FIFO (FIFORST bit in MMCFIFOCTL).
7.Set the FIFO direction to receive (FIFODIR bit in MMCFIFOCTL).
8.Set the access width (ACCWD bits in MMCFIFOCTL).
9.Set the FIFO threshold (FIFOLEV bit in MMCFIFOCTL).
10.Enable the MMC interrupt.
11.Enable the DRRDYINT interrupt.
12.Use MMCCMD to send the READ_SINGLE_BLOCK command.
13.Wait for the MMC interrupt.
14.Use the MMC status register 0 (MMCST0) to check for errors and the status of the FIFO. If the FIFO is not empty, go to step 15. If the all of the data has been read, stop.
15.Read the next n bytes of data (this depends on the setting of the FIFOLEV bit in MMCFIFOCTL:
0 = 16 bytes, 1 = 32 bytes) from the MMC data receive register (MMCDRR) and go to step 13.
The sequence of events in this operation is shown in Figure 15.
34 | Multimedia Card (MMC)/Secure Digital (SD) Card Controller | SPRUE30B |
