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Peripheral Architecture
2.5Data Flow in the Data Registers (MMCDRR and MMCDXR)
The CPU or EDMA controller can read 32 bits at a time from the FIFO by reading the MMC data receive register (MMCDRR) and write 32 bits at a time to the FIFO by writing to the MMC data transmit register (MMCDXR). However, since the memory card is an
Figure 8. Little-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA
FIFO
1st
2nd
3rd
4th
MMCDRR or MMCDXR registers
3 |
|
| 0 |
4th | 3rd | 2nd | 1st |
Support byten = ”1111”
1st
2nd
3rd
1st
2nd
3 |
|
| 0 |
| 3rd | 2nd | 1st |
Support byten = ”0111”
3 |
|
| 0 |
|
| 2nd | 1st |
Support byten = ”0011”
3
1st
0
1st
Support byten = ”0001”
SPRUE30B | Multimedia Card (MMC)/Secure Digital (SD) Card Controller | 17 |