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TMS320DM644x
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TMS320DM644x
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Functional Block Diagram
Signal Descriptions
Write-data CRC error
Reset Considerations
MMC Command Register Mmccmd
Power Management
Stream enable
MMC/SD Mode Write Sequence
Page 2
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SPRUE30B
–September
2006
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Contents
Users Guide
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Contents
Appendix a
List of Figures
List of Tables
Read This First
Trademarks
Purpose of the Peripheral
Features
Functional Block Diagram
Supported Use Case Statement
Industry Standards Compliance Statement
MMC/SD Controller Interface Diagram
MMC/SD Controller Clocking Diagram
Clock Control
1 MMC/SD Mode Write Sequence
Signal Descriptions
MMC/SD Controller Pins Used in Each Mode
Protocol Descriptions
Portion Sequence Description
MMC/SD Mode Write Sequence
2 MMC/SD Mode Read Sequence
CRC
MMC/SD Mode Read Sequence
Data Flow in the Input/Output Fifo
RD CMD
Fifo Operation Diagram
Data Flow in the Data Registers Mmcdrr and Mmcdxr
1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten =
1st 2nd 3rd 4th Support byten = 1111 1110
CPU Reads
Fifo Operation During Card Read Operation
Edma Reads
Fifo Operation During Card Read Diagram
CPU Writes
Fifo Operation During Card Write Operation
Edma Writes
Fifo Operation During Card Write Diagram
Reset Considerations
Initialization
Initialize the Time-Out Registers Mmctor and Mmctod
Initializing the Clock Controller Registers Mmcclk
Initialize the Interrupt Mask Register Mmcim
Initialize the Data Block Registers Mmcblen and Mmcnblk
Monitoring Activity in the MMC/SD Mode
Determining Whether New Data is Available in Mmcdrr
Checking For a Data Transmit Empty Condition
Interrupt Multiplexing
Interrupt Support
Interrupt Events and Requests
Description of MMC/SD Interrupt Requests
Emulation Considerations
Power Management
DMA Event Support
MMC Card Identification Procedure
Card Identification Operation
Procedures for Common Operations
SD Card Identification Procedure
MMC/SD Mode Single-Block Write Operation Using CPU
MMC/SD Mode Single-Block Write Operation
MMC/SD Mode Single-Block Write Operation Using the Edma
MMC/SD Mode Single-Block Read Operation Using the CPU
MMC/SD Mode Single-Block Read Operation Using Edma
MMC/SD Mode Single-Block Read Operation
MMC/SD Mode Multiple-Block Write Operation Using CPU
MMC/SD Multiple-Block Write Operation
MMC/SD Mode Multiple-Block Write Operation Using Edma
MMC/SD Mode Multiple-Block Read Operation Using CPU
MMC/SD Mode Multiple-Block Read Operation Using Edma
MMC/SD Mode Multiple-Block Read Operation
Offset Acronym Register Description
Bit Field Value Description
MMC Control Register Mmcctl
MMC Control Register Mmcctl Field Descriptions
Clken Clkrt
MMC Memory Clock Control Register Mmcclk
MMC Memory Clock Control Register Mmcclk Field Descriptions
Clken
Bit Field
MMC Status Register 0 MMCST0
MMC Status Register 0 MMCST0 Field Descriptions
Write-data CRC error
Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy
MMC Status Register 1 MMCST1
MMC Status Register 1 MMCST1 Field Descriptions
Fifoful
Etrndne Edated Edrrdy Edxrdy
MMC Interrupt Mask Register Mmcim
MMC Interrupt Mask Register Mmcim Field Descriptions
Etrndne
TOR
MMC Response Time-Out Register Mmctor
MMC Response Time-Out Register Mmctor Field Descriptions
MMC Data Read Time-Out Register Mmctod
MMC Data Read Time-Out Register Mmctod Field Descriptions
Blen
MMC Block Length Register Mmcblen
MMC Block Length Register Mmcblen Field Descriptions
MMC Number of Blocks Register Mmcnblk Field Descriptions
MMC Number of Blocks Register Mmcnblk
MMC Number of Blocks Counter Register Mmcnblc
Nblk
MMC Data Receive Register Mmcdrr Field Descriptions
MMC Data Receive Register Mmcdrr
MMC Data Transmit Register Mmcdxr
MMC Data Transmit Register Mmcdxr Field Descriptions
Dmatrig
MMC Command Register Mmccmd
MMC Command Register Mmccmd Field Descriptions
Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen
CRC7
Stream enable
Bit Position Command Register Description
Argh
MMC Argument Register Mmcarghl
MMC Argument Register Mmcarghl Field Descriptions
Argl
MMC Response Registers MMCRSP0-MMCRSP7
Bit Position of Response Register
R1, R3, R4, R5, or R6 Response 48 Bits
R2 Response 136 Bits
MMCRSP4-0
MMC Data Response Register Mmcdrsp
MMC Command Index Register Mmccidx
MMC Command Index Register Mmccidx Field Descriptions
MMC Data Response Register Mmcdrsp Field Descriptions
Accwd Fifolev Fifodir Fiforst
MMC Fifo Control Register Mmcfifoctl
MMC Fifo Control Register Mmcfifoctl Field Descriptions
Accwd
Table A-1. Document Revision History
Reference Additions/Modifications/Deletions
Appendix a
Important Notice