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Registers
4.18 MMC FIFO Control Register (MMCFIFOCTL)
The MMC FIFO control register (MMCFIFOCTL) is shown in Figure 39 and described in Table 25.
Figure 39. MMC FIFO Control Register (MMCFIFOCTL)
31 |
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| 16 |
| Reserved |
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15 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
| ACCWD | FIFOLEV | FIFODIR | FIFORST | |
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LEGEND: R/W = Read/Write; R = Read only;
Table 25. MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
ACCWD | Access width. Used by FIFO control to determine full/empty flag. | ||
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| 0 | CPU/EDMA access width of 4 bytes |
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| 1h | CPU/EDMA access width of 3 bytes |
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| 2h | CPU/EDMA access width of 2 bytes |
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| 3h | CPU/EDMA access width of 1 byte |
2 | FIFOLEV |
| FIFO level. Sets the threshold level that determines when the EDMA request and the FIFO threshold |
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| interrupt are triggered. |
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| 0 | EDMA request every 128 bits sent/received. |
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| 1 | EDMA request every 256 bits sent/received. |
1 | FIFODIR |
| FIFO direction. Determines if the FIFO is being written to or read from. |
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| 0 | Read from FIFO. |
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| 1 | Write to FIFO. |
0 | FIFORST |
| FIFO reset. Resets the internal state of the FIFO. |
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| 0 | FIFO reset is disabled. |
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| 1 | FIFO reset is enabled. |
58 | Multimedia Card (MMC)/Secure Digital (SD) Card Controller | SPRUE30B |
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