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Texas Instruments TMS320DM644x DMA Event Support, Power Management, Emulation Considerations

Models: TMS320DM644x

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Peripheral Architecture

2.11 DMA Event Support

The MMC/SD controller is capable of generating EDMA events for both read and write operations in order to request service from an EDMA controller. Based on the FIFO threshold setting, the EDMA event signals generate every time 128-bit or 256-bit data is transferred from the FIFO.

2.12 Power Management

You can put the MMC/SD peripheral in reduced-power modes to conserve power during periods of low activity. The processor power and sleep controller (PSC) controls the power management of the MMC/SD peripheral. The PSC acts as a master controller for power management for all of the peripherals on the device. For detailed information on power management procedures using the PSC, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (SPRUE14).

2.13 Emulation Considerations

The MMC/SD peripheral is not affected by emulation halt events (such as breakpoints).

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Multimedia Card (MMC)/Secure Digital (SD) Card Controller

SPRUE30B –September 2006

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Texas Instruments TMS320DM644x manual DMA Event Support, Power Management, Emulation Considerations

Contents

Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Supported Use Case Statement Industry Standards Compliance Statement MMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock Control Signal Descriptions MMC/SD Controller Pins Used in Each Mode1 MMC/SD Mode Write Sequence Protocol Descriptions 2 MMC/SD Mode Read Sequence MMC/SD Mode Write SequencePortion Sequence Description MMC/SD Mode Read Sequence Data Flow in the Input/Output FifoCRC RD CMD Fifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = 1st 2nd 3rd 4th Support byten = 1111 1110 Edma Reads Fifo Operation During Card Read OperationCPU Reads Fifo Operation During Card Read Diagram Edma Writes Fifo Operation During Card Write OperationCPU Writes Fifo Operation During Card Write Diagram Reset Considerations Initialization Initializing the Clock Controller Registers Mmcclk Initialize the Interrupt Mask Register MmcimInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and Mmcnblk Monitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in Mmcdrr Checking For a Data Transmit Empty Condition Interrupt Support Interrupt Events and RequestsInterrupt Multiplexing Description of MMC/SD Interrupt Requests DMA Event Support Power ManagementEmulation Considerations MMC Card Identification Procedure Card Identification Operation Procedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read Operation MMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Offset Acronym Register Description MMC Control Register Mmcctl Field Descriptions MMC Control Register MmcctlBit Field Value Description MMC Memory Clock Control Register Mmcclk MMC Memory Clock Control Register Mmcclk Field DescriptionsClken Clkrt Clken MMC Status Register 0 MMCST0 Field Descriptions MMC Status Register 0 MMCST0Bit Field Write-data CRC error MMC Status Register 1 MMCST1 MMC Status Register 1 MMCST1 Field DescriptionsFifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy Fifoful MMC Interrupt Mask Register Mmcim MMC Interrupt Mask Register Mmcim Field DescriptionsEtrndne Edated Edrrdy Edxrdy Etrndne MMC Response Time-Out Register Mmctor Field Descriptions MMC Response Time-Out Register MmctorTOR MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Block Length Register Mmcblen Field Descriptions MMC Block Length Register MmcblenBlen MMC Number of Blocks Register Mmcnblk MMC Number of Blocks Counter Register MmcnblcMMC Number of Blocks Register Mmcnblk Field Descriptions Nblk MMC Data Receive Register Mmcdrr MMC Data Transmit Register MmcdxrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field Descriptions MMC Command Register Mmccmd MMC Command Register Mmccmd Field DescriptionsDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen Bit Position Command Register Description Stream enableCRC7 MMC Argument Register Mmcarghl MMC Argument Register Mmcarghl Field DescriptionsArgh Argl MMC Response Registers MMCRSP0-MMCRSP7 R1, R3, R4, R5, or R6 Response 48 Bits R2 Response 136 BitsBit Position of Response Register MMCRSP4-0 MMC Command Index Register Mmccidx MMC Command Index Register Mmccidx Field DescriptionsMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field Descriptions MMC Fifo Control Register Mmcfifoctl MMC Fifo Control Register Mmcfifoctl Field DescriptionsAccwd Fifolev Fifodir Fiforst Accwd Table A-1. Document Revision History Reference Additions/Modifications/Deletions Appendix a Important Notice