Manuals / Texas Instruments / Photography / Camera Accessories

Texas Instruments TMS320DM644x manual MMC Argument Register Mmcarghl, Argh, Argl

Models: TMS320DM644x

1 61

Download 61 pages 29.83 Kb

Page 54

www.ti.com

Registers

4.14 MMC Argument Register (MMCARGHL)

Note: Do not modify the MMC argument register (MMCARGHL) while it is being used for an operation.

The MMC argument register (MMCARGHL) specifies the arguments to be sent with the command specified in the MMC command register (MMCCMD). Writing to MMCCMD causes the MMC controller to send a command; therefore, MMCARGHL must be configured before writing to MMCCMD. The content of MMCARGHL is kept after the transfer to the shift register; however, modification to MMCARGHL is not allowed during a sending operation. For the format of a command, see Figure 31 and Table 19.

The MMC argument register (MMCARGHL) is shown in Figure 32 and described in Table 20.

	Figure 32. MMC Argument Register (MMCARGHL)
31	16
	ARGH
	R/W-0
15	0

ARGL

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

Table 20. MMC Argument Register (MMCARGHL) Field Descriptions

Bit	Field	Value	Description
31-16	ARGH	0-FFFFh	Argument, high part.
15-0	ARGL	0-FFFFh	Argument, low part.

54	Multimedia Card (MMC)/Secure Digital (SD) Card Controller	SPRUE30B –September 2006
		Submit Documentation Feedback

Image 54

Texas Instruments TMS320DM644x manual MMC Argument Register Mmcarghl Field Descriptions, Argh, Argl

Contents

Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Features Functional Block DiagramPurpose of the Peripheral Supported Use Case Statement Industry Standards Compliance Statement MMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock Control 1 MMC/SD Mode Write Sequence Signal DescriptionsMMC/SD Controller Pins Used in Each Mode Protocol Descriptions MMC/SD Mode Write Sequence 2 MMC/SD Mode Read SequencePortion Sequence Description CRC MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo RD CMD Fifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = 1st 2nd 3rd 4th Support byten = 1111 1110 Fifo Operation During Card Read Operation Edma ReadsCPU Reads Fifo Operation During Card Read Diagram Fifo Operation During Card Write Operation Edma WritesCPU Writes Fifo Operation During Card Write Diagram Reset Considerations Initialization Initialize the Time-Out Registers Mmctor and Mmctod Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Data Block Registers Mmcblen and Mmcnblk Monitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in Mmcdrr Checking For a Data Transmit Empty Condition Interrupt Multiplexing Interrupt SupportInterrupt Events and Requests Description of MMC/SD Interrupt Requests Power Management DMA Event SupportEmulation Considerations MMC Card Identification Procedure Card Identification Operation Procedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read Operation MMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Offset Acronym Register Description MMC Control Register Mmcctl MMC Control Register Mmcctl Field DescriptionsBit Field Value Description Clken Clkrt MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions Clken MMC Status Register 0 MMCST0 MMC Status Register 0 MMCST0 Field DescriptionsBit Field Write-data CRC error Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions Fifoful Etrndne Edated Edrrdy Edxrdy MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions Etrndne MMC Response Time-Out Register Mmctor MMC Response Time-Out Register Mmctor Field DescriptionsTOR MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Block Length Register Mmcblen MMC Block Length Register Mmcblen Field DescriptionsBlen MMC Number of Blocks Register Mmcnblk Field Descriptions MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc Nblk MMC Data Receive Register Mmcdrr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Transmit Register Mmcdxr Field Descriptions Dmatrig MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen Stream enable Bit Position Command Register DescriptionCRC7 Argh MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions Argl MMC Response Registers MMCRSP0-MMCRSP7 Bit Position of Response Register R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits MMCRSP4-0 MMC Data Response Register Mmcdrsp MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register Mmcdrsp Field Descriptions Accwd Fifolev Fifodir Fiforst MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions Accwd Table A-1. Document Revision History Reference Additions/Modifications/Deletions Appendix a Important Notice