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Texas Instruments TMS320DM644x manual MMC Status Register 1 MMCST1, Fifoful

Models: TMS320DM644x

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Registers

4.4MMC Status Register 1 (MMCST1)

The MMC status register 1 (MMCST1) records specific events or errors. There are no interrupts associated with these events or errors.

The MMC status register 1 (MMCST1) is shown in Figure 21 and described in Table 9.

		Figure 21. MMC Status Register 1 (MMCST1)
31							16
			Reserved
			R-0
15							8
			Reserved
			R-0
7	6	5	4	3	2	1	0
Reserved	FIFOFUL	FIFOEMP	DAT3ST	DRFUL	DXEMP	CLKSTP	BUSY
R-0	R-0	R-0	R-0	R-0	R-0	R-1	R-0
LEGEND: R = Read only; -n= value after reset

			Table 9. MMC Status Register 1 (MMCST1) Field Descriptions
Bit	Field	Value	Description
31-7	Reserved	0	Reserved
6	FIFOFUL		FIFO is full.
		0	FIFO is not full.
		1	FIFO is full.
5	FIFOEMP		FIFO is empty.
		0	FIFO is not empty.
		1	FIFO is empty.
4	DAT3ST		DAT3 status.
		0	The signal level on the DAT3 pin is a logic-low level.
		1	The signal level on the DAT3 pin is a logic-high level.
3	DRFUL		Data receive register (MMCDRR) is full.
		0	A data receive register full condition is not detected. The data receive shift register is not full.

1A data receive register full condition is detected. The data receive shift register is full. No new bits can be shifted in from the memory card.

2	DXEMP	Data transmit register (MMCDXR) is empty.
	0	A data transmit register empty condition is not detected. The data transmit shift register is not empty.

1A data transmit register empty condition is detected. The data transmit shift register is empty. No bits are available to be shifted out to the memory card.

1	CLKSTP	Clock stop status.
	0	CLK is active. The memory clock signal is being driven on the pin.
	1	CLK is held low because of a manual stop (CLKEN = 0 in MMCCLK), receive shift register is full, or
		transmit shift register is empty.
0	BUSY	Busy.
	0	No busy signal is detected.
	1	A busy signal is detected (the memory card is busy).

SPRUE30B –September 2006	Multimedia Card (MMC)/Secure Digital (SD) Card Controller	45
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Texas Instruments TMS320DM644x manual MMC Status Register 1 MMCST1 Field Descriptions, Fifoful

Contents

Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Supported Use Case Statement MMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking Diagram MMC/SD Controller Pins Used in Each Mode Signal Descriptions1 MMC/SD Mode Write Sequence Protocol Descriptions MMC/SD Mode Write Sequence 2 MMC/SD Mode Read SequencePortion Sequence Description Data Flow in the Input/Output Fifo MMC/SD Mode Read SequenceCRC RD CMD Fifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Support byten = 1111 1110 Fifo Operation During Card Read Operation Edma ReadsCPU Reads Fifo Operation During Card Read Diagram Fifo Operation During Card Write Operation Edma WritesCPU Writes Fifo Operation During Card Write Diagram Initialization Reset Considerations Initialize the Interrupt Mask Register Mmcim Initializing the Clock Controller Registers MmcclkInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and Mmcnblk Determining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD Mode Checking For a Data Transmit Empty Condition Interrupt Events and Requests Interrupt SupportInterrupt Multiplexing Description of MMC/SD Interrupt Requests Power Management DMA Event SupportEmulation Considerations Card Identification Operation MMC Card Identification Procedure Procedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using Edma Offset Acronym Register Description MMC Control Register Mmcctl MMC Control Register Mmcctl Field DescriptionsBit Field Value Description MMC Memory Clock Control Register Mmcclk Field Descriptions MMC Memory Clock Control Register MmcclkClken Clkrt Clken MMC Status Register 0 MMCST0 MMC Status Register 0 MMCST0 Field DescriptionsBit Field Write-data CRC error MMC Status Register 1 MMCST1 Field Descriptions MMC Status Register 1 MMCST1Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy Fifoful MMC Interrupt Mask Register Mmcim Field Descriptions MMC Interrupt Mask Register MmcimEtrndne Edated Edrrdy Edxrdy Etrndne MMC Response Time-Out Register Mmctor MMC Response Time-Out Register Mmctor Field DescriptionsTOR MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register Mmctod MMC Block Length Register Mmcblen MMC Block Length Register Mmcblen Field DescriptionsBlen MMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register MmcnblkMMC Number of Blocks Register Mmcnblk Field Descriptions Nblk MMC Data Transmit Register Mmcdxr MMC Data Receive Register MmcdrrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field Descriptions MMC Command Register Mmccmd Field Descriptions MMC Command Register MmccmdDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen Stream enable Bit Position Command Register DescriptionCRC7 MMC Argument Register Mmcarghl Field Descriptions MMC Argument Register MmcarghlArgh Argl MMC Response Registers MMCRSP0-MMCRSP7 R2 Response 136 Bits R1, R3, R4, R5, or R6 Response 48 BitsBit Position of Response Register MMCRSP4-0 MMC Command Index Register Mmccidx Field Descriptions MMC Command Index Register MmccidxMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field Descriptions MMC Fifo Control Register Mmcfifoctl Field Descriptions MMC Fifo Control Register MmcfifoctlAccwd Fifolev Fifodir Fiforst Accwd Reference Additions/Modifications/Deletions Table A-1. Document Revision History Appendix a Important Notice