Tor | Texas Instruments TMS320DM644x specification

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Registers

Table 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions (continued)

Bit	Field	Value	Description
3	ETOUTRD		Read-data time-out event (TOUTRD) interrupt enable.
		0	Read-data time-out event interrupt is disabled.
		1	Read-data time-out event interrupt is enabled.
2	ERSPDNE		Command/response done (RSPDNE) interrupt enable.
		0	Command/response done interrupt is disabled.
		1	Command/response done interrupt is enabled.
1	EBSYDNE		Busy done (BSYDNE) interrupt enable.
		0	Busy done interrupt is disabled.
		1	Busy done interrupt is enabled.
0	EDATDNE		Data done (DATDNE) interrupt enable.
		0	Data done interrupt is disabled.
		1	Data done interrupt is enabled.

4.6MMC Response Time-Out Register (MMCTOR)

The MMC response time-out register (MMCTOR) defines how long the MMC controller waits for a response from a memory card before recording a time-out condition in the TOUTRS bit of the MMC status register 0 (MMCST0). If the corresponding ETOUTRS bit in the MMC interrupt mask register (MMCIM) is set, an interrupt is generated when the TOUTRS bit is set in MMCST0. If a memory card should require a longer time-out period than MMCTOR can provide, a software time-out mechanism can be implemented.

The MMC response time-out register (MMCTOR) is shown in Figure 23 and described in Table 11.

Figure 23. MMC Response Time-Out Register (MMCTOR)

31					16
			Reserved
				R-0
15	13	12	8	7	0
	Reserved		TOD_20_16		TOR
	R-0		R/W-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 11. MMC Response Time-Out Register (MMCTOR) Field Descriptions

Bit	Field	Value	Description
31-13	Reserved	0	Reserved
12-8	TOD_20_16	0-1Fh	Data read time-out count upper 5 bits. Used in conjunction with the TOD_15_0 bits in MMCTOD to
			form a 21-bit count. See MMCTOD (Section 4.7).
7-0	TOR	0-FFh	Time-out count for response.
		0	No time out
		1-FFh	1 CLK clock cycle to 255 CLK clock cycles

SPRUE30B –September 2006	Multimedia Card (MMC)/Secure Digital (SD) Card Controller	47
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Texas Instruments TMS320DM644x manual MMC Response Time-Out Register Mmctor, Tor

Contents

Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Supported Use Case Statement MMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking Diagram Protocol Descriptions Signal DescriptionsMMC/SD Controller Pins Used in Each Mode 1 MMC/SD Mode Write Sequence Portion Sequence Description MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence RD CMD MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo CRC Fifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Support byten = 1111 1110 CPU Reads Fifo Operation During Card Read OperationEdma Reads Fifo Operation During Card Read Diagram CPU Writes Fifo Operation During Card Write OperationEdma Writes Fifo Operation During Card Write Diagram Initialization Reset Considerations Initialize the Data Block Registers Mmcblen and Mmcnblk Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Time-Out Registers Mmctor and Mmctod Determining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD Mode Checking For a Data Transmit Empty Condition Description of MMC/SD Interrupt Requests Interrupt SupportInterrupt Events and Requests Interrupt Multiplexing Emulation Considerations Power ManagementDMA Event Support Card Identification Operation MMC Card Identification Procedure Procedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using Edma Offset Acronym Register Description Bit Field Value Description MMC Control Register MmcctlMMC Control Register Mmcctl Field Descriptions Clken MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions Clken Clkrt Bit Field MMC Status Register 0 MMCST0MMC Status Register 0 MMCST0 Field Descriptions Write-data CRC error Fifoful MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy Etrndne MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions Etrndne Edated Edrrdy Edxrdy TOR MMC Response Time-Out Register MmctorMMC Response Time-Out Register Mmctor Field Descriptions MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register Mmctod Blen MMC Block Length Register MmcblenMMC Block Length Register Mmcblen Field Descriptions Nblk MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register Mmcnblk Field Descriptions MMC Data Transmit Register Mmcdxr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Receive Register Mmcdrr Field Descriptions Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions Dmatrig CRC7 Stream enableBit Position Command Register Description Argl MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions Argh MMC Response Registers MMCRSP0-MMCRSP7 MMCRSP4-0 R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits Bit Position of Response Register MMC Data Response Register Mmcdrsp Field Descriptions MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register Mmcdrsp Accwd MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions Accwd Fifolev Fifodir Fiforst Reference Additions/Modifications/Deletions Table A-1. Document Revision History Appendix a Important Notice