Texas Instruments TMS320DM644x specification

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Procedures for Common Operations

Figure 16. MMC/SD Multiple-Block Write Operation

MMC controller register content

RCA ADDRESS HIGH

RCA ADDRESS LOW

SEL/DESEL. CARD

BLK ADDRESS HIGH

BLK ADDRESS LOW

SET_BLOCKLEN

READ_SINGLE_BLOCK

Is CRCWR = 1?

Is DXRDY = 1?

NEXT DATA BYTE

STOP_TRANSMISSION

MMC controller

register

ARG HIGH

ARG LOW

COMMAND

ARG HIGH

ARG LOW

COMMAND

COMMAND

STATUS 0

DATA TX

COMMAND

Select one card with relative card address (RCA) while de−selecting the other cards.

Load starting block address into the high and low argument registers. Load block

length register. Start the operation by loading a

READ_SINGLE_BLOCK command into the command register.

Check CRCWR bit for any write CRC errors.

Check DXRDY to see if a new byte can be put in MMCDXR register.

Terminate the multiple−block write operation.

SPRUE30B –September 2006

Multimedia Card (MMC)/Secure Digital (SD) Card Controller

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Texas Instruments TMS320DM644x manual MMC/SD Multiple-Block Write Operation

Contents

Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Supported Use Case Statement MMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking Diagram MMC/SD Controller Pins Used in Each Mode Signal Descriptions1 MMC/SD Mode Write Sequence Protocol Descriptions 2 MMC/SD Mode Read Sequence MMC/SD Mode Write SequencePortion Sequence Description Data Flow in the Input/Output Fifo MMC/SD Mode Read SequenceCRC RD CMD Fifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Support byten = 1111 1110 Edma Reads Fifo Operation During Card Read OperationCPU Reads Fifo Operation During Card Read Diagram Edma Writes Fifo Operation During Card Write OperationCPU Writes Fifo Operation During Card Write Diagram Initialization Reset Considerations Initialize the Interrupt Mask Register Mmcim Initializing the Clock Controller Registers MmcclkInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and Mmcnblk Determining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD Mode Checking For a Data Transmit Empty Condition Interrupt Events and Requests Interrupt SupportInterrupt Multiplexing Description of MMC/SD Interrupt Requests DMA Event Support Power ManagementEmulation Considerations Card Identification Operation MMC Card Identification Procedure Procedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using Edma Offset Acronym Register Description MMC Control Register Mmcctl Field Descriptions MMC Control Register MmcctlBit Field Value Description MMC Memory Clock Control Register Mmcclk Field Descriptions MMC Memory Clock Control Register MmcclkClken Clkrt Clken MMC Status Register 0 MMCST0 Field Descriptions MMC Status Register 0 MMCST0Bit Field Write-data CRC error MMC Status Register 1 MMCST1 Field Descriptions MMC Status Register 1 MMCST1Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy Fifoful MMC Interrupt Mask Register Mmcim Field Descriptions MMC Interrupt Mask Register MmcimEtrndne Edated Edrrdy Edxrdy Etrndne MMC Response Time-Out Register Mmctor Field Descriptions MMC Response Time-Out Register MmctorTOR MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register Mmctod MMC Block Length Register Mmcblen Field Descriptions MMC Block Length Register MmcblenBlen MMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register MmcnblkMMC Number of Blocks Register Mmcnblk Field Descriptions Nblk MMC Data Transmit Register Mmcdxr MMC Data Receive Register MmcdrrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field Descriptions MMC Command Register Mmccmd Field Descriptions MMC Command Register MmccmdDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen Bit Position Command Register Description Stream enableCRC7 MMC Argument Register Mmcarghl Field Descriptions MMC Argument Register MmcarghlArgh Argl MMC Response Registers MMCRSP0-MMCRSP7 R2 Response 136 Bits R1, R3, R4, R5, or R6 Response 48 BitsBit Position of Response Register MMCRSP4-0 MMC Command Index Register Mmccidx Field Descriptions MMC Command Index Register MmccidxMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field Descriptions MMC Fifo Control Register Mmcfifoctl Field Descriptions MMC Fifo Control Register MmcfifoctlAccwd Fifolev Fifodir Fiforst Accwd Reference Additions/Modifications/Deletions Table A-1. Document Revision History Appendix a Important Notice