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SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

SPRAAA6 — EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This document summarizes the key differences between the EDMA3 and the EDMA2 and provides guidance for migrating from EDMA2 to EDMA3.

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SPRUE30B –September 2006

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Texas Instruments TMS320DM644x manual Trademarks

Contents

Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Supported Use Case Statement Industry Standards Compliance Statement MMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock Control Signal Descriptions MMC/SD Controller Pins Used in Each Mode1 MMC/SD Mode Write Sequence Protocol Descriptions Portion Sequence Description MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence MMC/SD Mode Read Sequence Data Flow in the Input/Output FifoCRC RD CMD Fifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = 1st 2nd 3rd 4th Support byten = 1111 1110 CPU Reads Fifo Operation During Card Read OperationEdma Reads Fifo Operation During Card Read Diagram CPU Writes Fifo Operation During Card Write OperationEdma Writes Fifo Operation During Card Write Diagram Reset Considerations Initialization Initializing the Clock Controller Registers Mmcclk Initialize the Interrupt Mask Register MmcimInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and Mmcnblk Monitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in Mmcdrr Checking For a Data Transmit Empty Condition Interrupt Support Interrupt Events and RequestsInterrupt Multiplexing Description of MMC/SD Interrupt Requests Emulation Considerations Power ManagementDMA Event Support MMC Card Identification Procedure Card Identification Operation Procedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read Operation MMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Offset Acronym Register Description Bit Field Value Description MMC Control Register MmcctlMMC Control Register Mmcctl Field Descriptions MMC Memory Clock Control Register Mmcclk MMC Memory Clock Control Register Mmcclk Field DescriptionsClken Clkrt Clken Bit Field MMC Status Register 0 MMCST0MMC Status Register 0 MMCST0 Field Descriptions Write-data CRC error MMC Status Register 1 MMCST1 MMC Status Register 1 MMCST1 Field DescriptionsFifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy Fifoful MMC Interrupt Mask Register Mmcim MMC Interrupt Mask Register Mmcim Field DescriptionsEtrndne Edated Edrrdy Edxrdy Etrndne TOR MMC Response Time-Out Register MmctorMMC Response Time-Out Register Mmctor Field Descriptions MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field Descriptions Blen MMC Block Length Register MmcblenMMC Block Length Register Mmcblen Field Descriptions MMC Number of Blocks Register Mmcnblk MMC Number of Blocks Counter Register MmcnblcMMC Number of Blocks Register Mmcnblk Field Descriptions Nblk MMC Data Receive Register Mmcdrr MMC Data Transmit Register MmcdxrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field Descriptions MMC Command Register Mmccmd MMC Command Register Mmccmd Field DescriptionsDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen CRC7 Stream enableBit Position Command Register Description MMC Argument Register Mmcarghl MMC Argument Register Mmcarghl Field DescriptionsArgh Argl MMC Response Registers MMCRSP0-MMCRSP7 R1, R3, R4, R5, or R6 Response 48 Bits R2 Response 136 BitsBit Position of Response Register MMCRSP4-0 MMC Command Index Register Mmccidx MMC Command Index Register Mmccidx Field DescriptionsMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field Descriptions MMC Fifo Control Register Mmcfifoctl MMC Fifo Control Register Mmcfifoctl Field DescriptionsAccwd Fifolev Fifodir Fiforst Accwd Table A-1. Document Revision History Reference Additions/Modifications/Deletions Appendix a Important Notice