MMC/SD Mode Write Sequence | Texas Instruments TMS320DM644x guide

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Peripheral Architecture

Figure 5. MMC/SD Mode Write Sequence Timing Diagram

CMD
			Busy
2 CRC bytes			low
Data
Start	End	Start	End
bit	bit	bit	bit

CLK

	Table 2. MMC/SD Mode Write Sequence
Portion of the
Sequence	Description
WR CMD	Write command: A 6-byte WRITE_BLOCK command token is sent from the ARM to the card.
CMD RSP	Command response: The card sends a 6-byte response of type R1 to acknowledge the WRITE_BLOCK to the
	ARM.
DAT BLK	Data block: The ARM writes a block of data to the card. The data content is preceded by one start bit and is
	followed by two CRC bytes and one end bit.
CRC STAT	CRC status: The card sends a one byte CRC status information, which indicates to the ARM whether the data has
	been accepted by the card or rejected due to a CRC error. The CRC status information is preceded by one start
	bit and is followed by one end bit.
BSY	BUSY bit: The CRC status information is followed by a continuous stream of low busy bits until all of the data has
	been programmed into the flash memory on the card.

2.3.2MMC/SD Mode Read Sequence

Figure 6 and Table 3 show the signal activity when the MMC controller is in the MMC/SD mode and is reading data from a memory card. The same block length must be defined in the MMC controller and in the memory card before initiating a data read. In a successful read protocol sequence, the following steps occur:

∙The MMC/SD controller requests for the CSD content.

∙The card receives the command and sends the content of the CSD register as its response.

∙If the desired block length, READ_BL_LEN value, is different from the default value determined from the response, the MMC/SD controller sends the block length command.

∙The card receives the command and sends responses to the command.

∙The MMC/SD controller requests the card to change state from stand-by to transfer.

∙The card receives the command and sends responses to the command.

∙The MMC/SD controller sends a read command to the card.

∙The card drives responses to the command.

∙The card sends a block of data to the ARM.

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Multimedia Card (MMC)/Secure Digital (SD) Card Controller

SPRUE30B –September 2006

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Texas Instruments TMS320DM644x manual MMC/SD Mode Write Sequence, 2 MMC/SD Mode Read Sequence, Portion Sequence Description

Contents

Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Supported Use Case Statement Industry Standards Compliance Statement MMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock Control 1 MMC/SD Mode Write Sequence Signal DescriptionsMMC/SD Controller Pins Used in Each Mode Protocol Descriptions Portion Sequence Description MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence CRC MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo RD CMD Fifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = 1st 2nd 3rd 4th Support byten = 1111 1110 CPU Reads Fifo Operation During Card Read OperationEdma Reads Fifo Operation During Card Read Diagram CPU Writes Fifo Operation During Card Write OperationEdma Writes Fifo Operation During Card Write Diagram Reset Considerations Initialization Initialize the Time-Out Registers Mmctor and Mmctod Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Data Block Registers Mmcblen and Mmcnblk Monitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in Mmcdrr Checking For a Data Transmit Empty Condition Interrupt Multiplexing Interrupt SupportInterrupt Events and Requests Description of MMC/SD Interrupt Requests Emulation Considerations Power ManagementDMA Event Support MMC Card Identification Procedure Card Identification Operation Procedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read Operation MMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Offset Acronym Register Description Bit Field Value Description MMC Control Register MmcctlMMC Control Register Mmcctl Field Descriptions Clken Clkrt MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions Clken Bit Field MMC Status Register 0 MMCST0MMC Status Register 0 MMCST0 Field Descriptions Write-data CRC error Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions Fifoful Etrndne Edated Edrrdy Edxrdy MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions Etrndne TOR MMC Response Time-Out Register MmctorMMC Response Time-Out Register Mmctor Field Descriptions MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field Descriptions Blen MMC Block Length Register MmcblenMMC Block Length Register Mmcblen Field Descriptions MMC Number of Blocks Register Mmcnblk Field Descriptions MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc Nblk MMC Data Receive Register Mmcdrr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Transmit Register Mmcdxr Field Descriptions Dmatrig MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen CRC7 Stream enableBit Position Command Register Description Argh MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions Argl MMC Response Registers MMCRSP0-MMCRSP7 Bit Position of Response Register R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits MMCRSP4-0 MMC Data Response Register Mmcdrsp MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register Mmcdrsp Field Descriptions Accwd Fifolev Fifodir Fiforst MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions Accwd Table A-1. Document Revision History Reference Additions/Modifications/Deletions Appendix a Important Notice