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TMS320DM644x manual
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61 pages, 669.83 Kb
TMS320DM644x DMSoC
Multimedia
Card (MMC)/Secure
Digital
(SD)
Card Controller
User's Guide
Literature
Number: SPRUE30B
September 2006
Contents
Main
Page
Contents
Page
Page
Page
Preface
Read This First
Page
User's Guide
Multimedia Card (MMC)/Secure Digital (SD) CardController
1.4 Supported Use Case Statement
1.5 Industry Standard(s) Compliance Statement
2 Peripheral Architecture
Figure 2. MMC/SD Controller Interface Diagram
Figure 3. MMC Configuration and SD Configuration Diagram
2.1 Clock Control
2.2 Signal Descriptions
2.3 Protocol Descriptions
Page
2.4 Data Flow in the Input/Output FIFO
Figure 6. MMC/SD Mode Read Sequence Timing Diagram
Table 3. MMC/SD Mode Read Sequence
Page
2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR)
Figure 9. Big-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA
2.6 FIFO Operation During Card Read Operation
Figure 10. FIFO Operation During Card Read Diagram
2.7 FIFO Operation During Card Write Operation
Figure 11. FIFO Operation During Card Write Diagram
2.8 Reset Considerations
2.9 Initialization
Page
Page
Page
2.10 Interrupt Support
Page
3 Procedures for Common Operations 3.1 Card Identification Operation
Page
Page
3.2 MMC/SD Mode Single-Block Write Operation Using CPU
Procedures for Common Operations
Figure 14. MMC/SD Mode Single-Block Write Operation
3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA
3.4 MMC/SD Mode Single-Block Read Operation Using the CPU
3.5 MMC/SD Mode Single-Block Read Operation Using EDMA
3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU
Procedures for Common Operations
Figure 16. MMC/SD Multiple-Block Write Operation
3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA
3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU
3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA
4 Registers
4.1 MMC Control Register (MMCCTL)
Table 6. MMC Control Register (MMCCTL) Field Descriptions
4.2 MMC Memory Clock Control Register (MMCCLK)
4.3 MMC Status Register 0 (MMCST0)
Table 8. MMC Status Register 0 (MMCST0) Field Descriptions
Table 8. MMC Status Register 0 (MMCST0) Field Descriptions (continued)
4.4 MMC Status Register 1 (MMCST1)
Table 9. MMC Status Register 1 (MMCST1) Field Descriptions
4.5 MMC Interrupt Mask Register (MMCIM)
Table 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions
4.6 MMC Response Time-Out Register (MMCTOR)
Table 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions (continued)
Table 11. MMC Response Time-Out Register (MMCTOR) Field Descriptions
4.7 MMC Data Read Time-Out Register (MMCTOD)
4.8 MMC Block Length Register (MMCBLEN)
4.9 MMC Number of Blocks Register (MMCNBLK)
4.10 MMC Number of Blocks Counter Register (MMCNBLC)
4.11 MMC Data Receive Register (MMCDRR)
4.12 MMC Data Transmit Register (MMCDXR)
4.13 MMC Command Register (MMCCMD)
Table 18. MMC Command Register (MMCCMD) Field Descriptions
Table 18. MMC Command Register (MMCCMD) Field Descriptions (continued)
Figure 31. Command Format
Table 19. Command Format
4.14 MMC Argument Register (MMCARGHL)
4.15 MMC Response Registers (MMCRSP0-MMCRSP7)
Figure 34. MMC Response Register 2 and 3 (MMCRSP23)
Figure 35. MMC Response Register 4 and 5 (MMCRSP45)
Figure 36. MMC Response Register 6 and 7 (MMCRSP67)
Table 21. R1, R3, R4, R5, or R6 Response (48 Bits)
Bits 7-0 of the response are stored to bits 7-0 of MMCRSP5. Table 22. R2 Response (136 Bits)
4.16 MMC Data Response Register (MMCDRSP)
4.17 MMC Command Index Register (MMCCIDX)
4.18 MMC FIFO Control Register (MMCFIFOCTL)
Table 25. MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions
Appendix A Revision History
Appendix A
