![](/images/new-backgrounds/1178676/17867611x1.webp)
| List of Tables |
|
1 | MMC/SD Controller Pins Used in Each Mode | 13 |
2 | MMC/SD Mode Write Sequence | 14 |
3 | MMC/SD Mode Read Sequence | 15 |
4 | Description of MMC/SD Interrupt Requests | 27 |
5 | Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers | 40 |
6 | MMC Control Register (MMCCTL) Field Descriptions | 41 |
7 | MMC Memory Clock Control Register (MMCCLK) Field Descriptions | 42 |
8 | MMC Status Register 0 (MMCST0) Field Descriptions | 43 |
9 | MMC Status Register 1 (MMCST1) Field Descriptions | 45 |
10 | MMC Interrupt Mask Register (MMCIM) Field Descriptions | 46 |
11 | MMC Response | 47 |
12 | MMC Data Read | 48 |
13 | MMC Block Length Register (MMCBLEN) Field Descriptions | 49 |
14 | MMC Number of Blocks Register (MMCNBLK) Field Descriptions | 50 |
15 | MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions | 50 |
16 | MMC Data Receive Register (MMCDRR) Field Descriptions | 51 |
17 | MMC Data Transmit Register (MMCDXR) Field Descriptions | 51 |
18 | MMC Command Register (MMCCMD) Field Descriptions | 52 |
19 | Command Format | 53 |
20 | MMC Argument Register (MMCARGHL) Field Descriptions | 54 |
21 | R1, R3, R4, R5, or R6 Response (48 Bits) | 56 |
22 | R2 Response (136 Bits) | 56 |
23 | MMC Data Response Register (MMCDRSP) Field Descriptions | 57 |
24 | MMC Command Index Register (MMCCIDX) Field Descriptions | 57 |
25 | MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions | 58 |
Document Revision History | 59 |
6 | List of Tables | SPRUE30B |