List of Figures | Texas Instruments TMS320DM644x manual

	List of Figures
1	MMC/SD Card Controller Block Diagram	10
2	MMC/SD Controller Interface Diagram	11
3	MMC Configuration and SD Configuration Diagram	11
4	MMC/SD Controller Clocking Diagram	12
5	MMC/SD Mode Write Sequence Timing Diagram	14
6	MMC/SD Mode Read Sequence Timing Diagram	15
7	FIFO Operation Diagram	16
8	Little-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA	17
9	Big-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA	18
10	FIFO Operation During Card Read Diagram	20
11	FIFO Operation During Card Write Diagram	22
12	MMC Card Identification Procedure	30
13	SD Card Identification Procedure	31
14	MMC/SD Mode Single-Block Write Operation	33
15	MMC/SD Mode Single-Block Read Operation	35
16	MMC/SD Multiple-Block Write Operation	37
17	MMC/SD Mode Multiple-Block Read Operation	39
18	MMC Control Register (MMCCTL)	41
19	MMC Memory Clock Control Register (MMCCLK)	42
20	MMC Status Register 0 (MMCST0)	43
21	MMC Status Register 1 (MMCST1)	45
22	MMC Interrupt Mask Register (MMCIM)	46
23	MMC Response Time-Out Register (MMCTOR)	47
24	MMC Data Read Time-Out Register (MMCTOD)	48
25	MMC Block Length Register (MMCBLEN)	49
26	MMC Number of Blocks Register (MMCNBLK)	50
27	MMC Number of Blocks Counter Register (MMCNBLC)	50
28	MMC Data Receive Register (MMCDRR)	51
29	MMC Data Transmit Register (MMCDXR)	51
30	MMC Command Register (MMCCMD)	52
31	Command Format	53
32	MMC Argument Register (MMCARGHL)	54
33	MMC Response Register 0 and 1 (MMCRSP01)	55
34	MMC Response Register 2 and 3 (MMCRSP23)	55
35	MMC Response Register 4 and 5 (MMCRSP45)	55
36	MMC Response Register 6 and 7 (MMCRSP67)	55
37	MMC Data Response Register (MMCDRSP)	57
38	MMC Command Index Register (MMCCIDX)	57
39	MMC FIFO Control Register (MMCFIFOCTL)	58

SPRUE30B –September 2006

List of Figures

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Texas Instruments TMS320DM644x manual List of Figures

Contents

Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Supported Use Case Statement MMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking Diagram MMC/SD Controller Pins Used in Each Mode Signal Descriptions1 MMC/SD Mode Write Sequence Protocol Descriptions Portion Sequence Description MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence Data Flow in the Input/Output Fifo MMC/SD Mode Read SequenceCRC RD CMD Fifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Support byten = 1111 1110 CPU Reads Fifo Operation During Card Read OperationEdma Reads Fifo Operation During Card Read Diagram CPU Writes Fifo Operation During Card Write OperationEdma Writes Fifo Operation During Card Write Diagram Initialization Reset Considerations Initialize the Interrupt Mask Register Mmcim Initializing the Clock Controller Registers MmcclkInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and Mmcnblk Determining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD Mode Checking For a Data Transmit Empty Condition Interrupt Events and Requests Interrupt SupportInterrupt Multiplexing Description of MMC/SD Interrupt Requests Emulation Considerations Power ManagementDMA Event Support Card Identification Operation MMC Card Identification Procedure Procedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using Edma Offset Acronym Register Description Bit Field Value Description MMC Control Register MmcctlMMC Control Register Mmcctl Field Descriptions MMC Memory Clock Control Register Mmcclk Field Descriptions MMC Memory Clock Control Register MmcclkClken Clkrt Clken Bit Field MMC Status Register 0 MMCST0MMC Status Register 0 MMCST0 Field Descriptions Write-data CRC error MMC Status Register 1 MMCST1 Field Descriptions MMC Status Register 1 MMCST1Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy Fifoful MMC Interrupt Mask Register Mmcim Field Descriptions MMC Interrupt Mask Register MmcimEtrndne Edated Edrrdy Edxrdy Etrndne TOR MMC Response Time-Out Register MmctorMMC Response Time-Out Register Mmctor Field Descriptions MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register Mmctod Blen MMC Block Length Register MmcblenMMC Block Length Register Mmcblen Field Descriptions MMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register MmcnblkMMC Number of Blocks Register Mmcnblk Field Descriptions Nblk MMC Data Transmit Register Mmcdxr MMC Data Receive Register MmcdrrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field Descriptions MMC Command Register Mmccmd Field Descriptions MMC Command Register MmccmdDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen CRC7 Stream enableBit Position Command Register Description MMC Argument Register Mmcarghl Field Descriptions MMC Argument Register MmcarghlArgh Argl MMC Response Registers MMCRSP0-MMCRSP7 R2 Response 136 Bits R1, R3, R4, R5, or R6 Response 48 BitsBit Position of Response Register MMCRSP4-0 MMC Command Index Register Mmccidx Field Descriptions MMC Command Index Register MmccidxMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field Descriptions MMC Fifo Control Register Mmcfifoctl Field Descriptions MMC Fifo Control Register MmcfifoctlAccwd Fifolev Fifodir Fiforst Accwd Reference Additions/Modifications/Deletions Table A-1. Document Revision History Appendix a Important Notice