![](/images/new-backgrounds/1178676/17867681x1.webp)
www.ti.com
Registers
4.1MMC Control Register (MMCCTL)
The MMC control register (MMCCTL) is used to enable or configure various modes of the MMC controller. Set or clear the DATRST and CMDRST bits at the same time to reset or enable the MMC controller.
The MMC control register (MMCCTL) is shown in Figure 18 and described in Table 6.
Figure 18. MMC Control Register (MMCCTL)
31 |
|
|
|
|
| 16 |
|
| Reserved |
|
|
|
|
|
|
|
|
|
| |
15 |
|
| 11 | 10 | 9 | 8 |
|
| Reserved |
| PERMDX | PERMDR | Reserved |
|
|
| ||||
7 | 6 | 5 | 3 | 2 | 1 | 0 |
| DATEG | Reserved |
| WIDTH | CMDRST | DATRST |
|
| |||||
LEGEND: R/W = Read/Write; R = Read only; |
|
|
|
|
|
|
| Table 6. MMC Control Register (MMCCTL) Field Descriptions |
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
10 | PERMDX |
| Endian select when writing. |
|
| 0 | Little endian is selected. |
|
| 1 | Big endian is selected. |
9 | PERMDR |
| Endian select when reading. |
|
| 0 | Little endian is selected. |
|
| 1 | Big endian is selected. |
8 | Reserved | 0 | Reserved |
DATEG | DAT3 edge detection select. | ||
|
| 0 | DAT3 edge detection is disabled. |
|
| 1h | DAT3 |
|
| 2h | DAT3 |
|
| 3h | DAT3 |
Reserved | 0 | Reserved | |
2 | WIDTH |
| Data bus width (MMC mode only). |
|
| 0 | Data bus has 1 bit (only DAT0 is used). |
|
| 1 | Data bus has 4 bits (all |
1 | CMDRST |
| CMD logic reset. |
|
| 0 | CMD line portion is enabled. |
|
| 1 | CMD line portion is disabled and in reset state. |
0 | DATRST |
| DAT logic reset. |
|
| 0 | DAT line portion is enabled. |
|
| 1 | DAT line portion is disabled and in reset state. |
SPRUE30B | Multimedia Card (MMC)/Secure Digital (SD) Card Controller | 41 |
Submit Documentation Feedback |
|
|