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Peripheral Architecture
Figure 11. FIFO Operation During Card Write Diagram
| FIFO Check1/Start |
|
|
Yes | FIFO |
|
|
| full |
|
|
| ? |
|
|
| No |
|
|
| Capture data, |
|
|
| no DMA pending |
|
|
| Increment counter |
|
|
No | Counter |
|
|
| =FIFOLEV |
|
|
| ? |
|
|
| Yes |
|
|
| Generate DMA |
|
|
| Reset counter |
|
|
| FIFO check 2 |
|
|
Yes | FIFO |
|
|
| full |
|
|
| ? |
|
|
| No |
|
|
| Capture data, |
|
|
| DMA |
|
|
| Increment counter |
| Idle, DMA pending |
| Counter | Yes |
|
| =FIFOLEV | No | DMA |
| ? |
| done |
|
|
| ? |
| No |
|
|
|
|
| Yes |
No | DMA |
| Generate DMA |
| done |
|
|
| ? |
| Reset counter |
|
|
| |
| Yes |
|
|
22 | Multimedia Card (MMC)/Secure Digital (SD) Card Controller | SPRUE30B |