Texas Instruments TNETX3270 specifications ThunderSWITCH 24/3 ETHERNET, Contents

		TNETX3270
		ThunderSWITCH 24/3 ETHERNET	SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
		SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999
	Contents
Description	2	SDRAM Interface	. . . . . . 36
PGV Package Terminal Layout	4	SDRAM-Type and Quantity Indication	. . . . . . 38
TNETX3270 Interface Block Diagram	5	Initialization	. . . . . . 38
Terminal Functions	6	Refresh	. . . . . . 38
DIO Register Groups	13	Frame Routing	. . . . . . 39
Interface Description	18	VLAN Support	. . . . . . 39
DIO Interface	18	IEEE Std 802.1Q Headers ± Reception	. . . . . . 40
Receiving/Transmitting Management Frames	18	IEEE Std 802.1Q Headers ± Transmission	. . . . . . 40
State of DIO Signals During Hardware Reset	18	Address Maintenance	. . . . . . 40
Network Management Port	19	Spanning-Tree Support	. . . . . . 41
MII Serial Management Interface (PHY Management) . . .	22	Aging Algorithms	. . . . . . 41
10-Mbit/s and 10-/100-Mbit/s MAC Interface	22	Frame-Routing Determination	. . . . . . 41
Receive Control	22	Port Mirroring	. . . . . . 44
Giant (Long) Frames	22	Port Trunking/Load Sharing	. . . . . . 45
Short Frames	22	Flow Control	. . . . . . 45
Receive Filtering of Frames	23	Collision-Based Flow Control	. . . . . . 46
Data Transmission	23	IEEE Std 802.3 Flow Control	. . . . . . 46
Transmit Control	23	Internal Wrap Test	. . . . . . 48
Adaptive Performance Optimization		Duplex Wrap Test	. . . . . . 49
(APO) (Transmit Pacing)	23	Port Mirroring	. . . . . . 50
Interframe Gap Enforcement	23	Copy to Uplink	. . . . . . 50
Backoff	23	Absolute Maximum Ratings	. . . . . . 51
Receive Versus Transmit Priority	24	Recommended Operating Conditions	. . . . . . 51
Uplink Pretagging	24	Electrical Characteristics	. . . . . . 51
EEPROM Interface	27	Parameter Measurement Information	. . . . . . 52
Interaction of EEPROM Load With the SIO Register . .	28	Test Measurement	. . . . . . 52
Summary of EEPROM Load Outcomes	28	10-Mbit/s Interface (Ports 00±23)	. . . . . . 53
Compatibility With Future Device Revisions	28	10-/100-Mbit/s MAC Interface	. . . . . . 54
JTAG Interface	29	SDRAM Interface	. . . . . . 56
HIGHZ instruction	29	DIO/DMA Interface	. . . . . . 58
LED Interface	29	Serial MII Management Interface	. . . . . . 60
Lamp Test	30	EEPROM Interface	. . . . . . 61
Multi-LED Display	30	LED Interface	. . . . . . 62
Hardware Configurations	30	Power-Up OSCIN and RESET	. . . . . . 63
10-Mbit/s MAC Interfaces (Ports 00±23)	30	Mechanical Data	. . . . . . 64
10-/100-Mbit/s MAC Interfaces (Ports 24±26)	34
10-/100-Mbit/s Port Configuration	34
10-/100-Mbit/s Port Configuration
in a Nonmanaged Switch	35
10-/100-Mbit/s Port Configuration
in a Managed Switch	36

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