TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999
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| 1 |
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THxCLK |
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(input) |
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| 2 | 2 |
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THxSYNC |
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(input) |
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THxCOL | 3 | 5 |
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THxCRS |
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THxLINK |
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THxRXD3±THxRXD0 |
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THxRXDV |
| 4 | 6 |
(inputs) |
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THxTXEN | 7 |
| 8 |
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THxTXD3±THxTXD0 |
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THxRENEG |
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(outputs) |
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Figure 13. 10-Mbit/s Interface (Ports 00±23)
10-/100-Mbit/s MAC interface
Figures 14 and 15 show the timings at 100 Mbit/s and 10 Mbit/s for the 10-/100-Mbit/s port interfaces to the TNETE2101 devices.
10-/100-Mbit/s receive ports (24, 25, 26)
timing requirements (see Note 7 and Figure 14)
NO. |
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| MIN | MAX | UNIT |
1 | tc(MxxRCLK) | Cycle time, MxxRCLK | 25 | 25 | ns |
2 | tw(MxxRCLKL) | Pulse duration, MxxRCLK low |
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| ns |
3 | tw(MxxRCLKH) | Pulse duration, MxxRCLK high | 14 |
| ns |
4² | t | Setup time, MxxRXD3±MxxRXD0 valid before MxxRCLK↑ | 5 |
| ns |
| su(MxxRXD) |
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4² | t | Setup time, MxxRXDV valid before MxxRCLK↑ | 5 |
| ns |
| su(MxxRXDV) |
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4² | t | Setup time, MxxRXER valid before MxxRCLK↑ | 5 |
| ns |
| su(MxxRXER) |
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5² | t | Hold time, MxxRXD3±MxxRXD0 valid after MxxRCLK↑ | 5 |
| ns |
| h(MxxRXD) |
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5² | t | Hold time, MxxRXDV valid after MxxRCLK↑ | 5 |
| ns |
| h(MxxRXDV) |
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5² | t | Hold time, MxxRXER valid after MxxRCLK↑ | 5 |
| ns |
| h(MxxRXER) |
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² xx = ports 24, 25, and 26
NOTE 7: Both MxxCRS and MxxCOL are driven asynchronously by the PHY. MxxRXD3±MxxRXD0 is driven by the PHY on the falling edge of
MxxRCLK. MxxRXD3±MxxRXD0 timing must be met during clock periods when MxxRXDV is asserted. MxxRXDV is asserted and deasserted by the PHY on the falling edge of MxxRCLK. MxxRXER is driven by the PHY on the falling edge of MxxRCLK.
| 1 |
4 | 5 |
2 | 2 |
MxxRCLK |
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(input) |
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MxxRXD3±MxxRXD0
MxxRXDV
MxxRXER
(inputs)
Figure 14. 10-/100-Mbit/s Receive Ports
54 | POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
