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Texas Instruments TNETX3270 10-/100-Mbit/s MAC interface, 10-/100-Mbit/s timing requirements (see Note 7 and Figure 14)

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TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THxCLK

(input)

THxSYNC

(input)

THxCOL

THxCRS

THxLINK

THxRXD3–THxRXD0

THxRXDV

(inputs)

THxTXEN

THxTXD3–THxTXD0

THxRENEG

(outputs)

1

2 2

53

64

8

7

Figure 13. 10-Mbit/s Interface (Ports 00–23)

10-/100-Mbit/s MAC interface

Figures 14 and 15 show the timings at 100 Mbit/s and 10 Mbit/s for the 10-/100-Mbit/s port interfaces to the

TNETE2101 devices.

10-/100-Mbit/s receive ports (24, 25, 26)

timing requirements (see Note 7 and Figure 14)

NO. MIN MAX UNIT

1 tc(MxxRCLK) Cycle time, MxxRCLK 25 25 ns

2 tw(MxxRCLKL) Pulse duration, MxxRCLK low ns

3 tw(MxxRCLKH) Pulse duration, MxxRCLK high 14 ns

4†tsu(MxxRXD) Setup time, MxxRXD3–MxxRXD0 valid before MxxRCLK↑5 ns

4†tsu(MxxRXDV) Setup time, MxxRXDV valid before MxxRCLK↑5 ns

4†tsu(MxxRXER) Setup time, MxxRXER valid before MxxRCLK↑5 ns

5†th(MxxRXD) Hold time, MxxRXD3–MxxRXD0 valid after MxxRCLK↑5 ns

5†th(MxxRXDV) Hold time, MxxRXDV valid after MxxRCLK↑5 ns

5†th(MxxRXER) Hold time, MxxRXER valid after MxxRCLK↑5 ns

†xx = ports 24, 25, and 26

NOTE 7: Both MxxCRS and MxxCOL are driven asynchronously by the PHY. MxxRXD3–MxxRXD0 is driven by the PHY on the falling edge of

MxxRCLK. MxxRXD3–MxxRXD0 timing must be met during clock periods when MxxRXDV is asserted. MxxRXDV is asserted and

deasserted by the PHY on the falling edge of MxxRCLK. MxxRXER is driven by the PHY on the falling edge of MxxRCLK.

MxxRXD3–MxxRXD0

MxxRXDV

MxxRXER

(inputs)

MxxRCLK

(input)

4 5

1

2 2

Figure 14. 10-/100-Mbit/s Receive Ports

Contents

Main TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS description TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B NOVEMBER 1997 REVISED APRIL 1999 PGV PACKAGE (TOP VIEW) ThunderSWITCH 24/3 ETHERNET SWITCH PRODUCT PREVIEW Figure 1. TNETX3270 Interface Block Diagram Page TNETX3270 10-/100-Mbit/s MAC interface (ports 2426) 10-/100-Mbit/s MAC interface (ports 2426) (continued) SDRAM interface WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS host DIO interface serial MII management PHY interface EEPROM interface LED interface JTAG interface miscellaneous power interface summary of signal terminals by signal group function DIO register groups Table 1. Internal Register and Statistics Memory Map Table 2. Detailed DIO Register Map Page Page Page interface description receiving/transmitting management frames state of DIO signals during hardware reset network management port Page Page receive control giant (long) frames short frames receive filtering of frames data transmission transmit control adaptive performance optimization (APO) (transmit pacing) interframe gap enforcement ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS receive versus transmit priority uplink pretagging Table 5. Source-Port Pretag Encoding Page TNETX3270 interaction of EEPROM load with the SIO register summary of EEPROM load outcomes compatibility with future device revisions HIGHZ instruction lamp test multi-LED display hardware configurations Page TNETX3270 Figure 6. 10-Mbit/s Interface-Port Signal Timing Figure 7. Connecting to TNETE2008 PHY 10-/100-Mbit/s port configuration 10-/100-Mbit/s port configuration (continued) 10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch SDRAM interface (continued) Table 15. TNETX3270 Terminal Interface to SDRAMs SDRAM-type and quantity indication initialization refresh 39 frame routing txacc Figure 8. VLAN Overview Transmit rxacc IEEE Std 802.1Q headers reception IEEE Std 802.1Q headers transmission address maintenance spanning-tree support aging algorithms frame-routing determination Unkmem Figure 9. Frame-Routing Algorithm interrupt UnkVLAN Figure 9. Frame-Routing Algorithm (Continued) new chng secvio Port Trunking/Load Sharing port mirroring port trunking/load sharing collision-based flow control IEEE Std 802.3 flow control Page internal wrap test duplex wrap test Page absolute maximum ratings over operating junction temperature range (unless otherwise noted) recommended operating conditions electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MEASUREMENT INFORMATION test measurement 10-Mbit/s interface (ports 0023) timing requirements (see Notes 3 through 6 and Figure 13) Figure 13. 10-Mbit/s Interface (Ports 0023) 10-/100-Mbit/s MAC interface Figure 14. 10-/100-Mbit/s Receive Ports 10-/100-Mbit/s timing requirements (see Note 7 and Figure 14) 10-/100-Mbit/s timing requirements (see Figure 15) operating characteristics over recommended operating conditions (see Note 8 and Figure 15) Figure 15. 10-/100-Mbit/s Transmit Ports SDRAM interface SDRAM subcycle operating characteristics over recommended operating conditions (see Figure 17) Figure 17. SDRAM Subcycle DIO/DMA interface Figure 18. DIO/DMA Write Cycle timing requirements (see Figure 18) operating characteristics over recommended operating conditions (see Figure 18) DIO/DMA read cycle timing requirements (see Figure 19) Figure 19. DIO/DMA Read Cycle operating characteristics over recommended operating conditions (see Figure 19) serial MII management interface timing requirements (see Figure 20) operating characteristics over recommended operating conditions (see Figure 20) Figure 20. Serial MII Management Read/Write Cycle EEPROM interface operating characteristics over recommended operating conditions (see Figure 21) Figure 21. EEPROM LED interface operating characteristics over recommended operating conditions (see Figure 22) Figure 22. LED power-up OSCIN and RESET timing requirements (see Figure 23) Figure 23. Power-Up OSCIN and RESET MECHANICAL DATA PGV (S-PQFP-G240) PLASTIC QUAD FLATPACK (DIEDOWN)