TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
frame format on the NM port (continued)
When a frame is transmitted on the NM port, no header stripping occurs (again because the NM port does not
have a PortxQtag register or
txacc bit), so the frame read by the host software contains one header (or possibly
more, depending on how the frame was received).
In either case, the NM port inserts its own port number into the source port field in the least significant bits of
the first TPID byte and sets the reserved bits to 0. Frames received from the host via the NM port are required
to contain a valid IEEE Std 802.1Q VLAN ID (VID) in the third and fourth bytes following the source address.
(The NM port does not have a default VLAN ID register for inserting a VLAN tag if none is provided. It cannot
also be configured as an access port.) Frames that do not contain a valid tag are incorrectly routed. They also
can be corrupted at the transmission port(s), as the tag-stripping process does not verify that the four bytes after
the source address are a valid tag because they are valid tags under all other circumstances.
When a frame is transmitted on (read from) the NM port, no tag stripping occurs (because the NM port does
not have the default VLAN ID register or access configuration control), so the frame read by the host software
can contain one or more header tags, depending on how the frame was received.
MII serial management interface (PHY management)
This interface gives the user an easy way to implement a software-controlled bit serial MII.
MII devices that implement the management interface, consisting of MDIO and MDCLK, can be accessed in
this way through the SIO register. The direction of MDIO is controlled by the SIO register. In addition, a third
signal, MRESET, is provided to allow hardware reset of PHYs that support it.
All three signals have internal pullup resistors, since they all can be placed into high impedance via the MDIOEN
bit of the SIO register, to allow another bus master.
The interface does not implement timing or data structure. The timing and frame format must be ensured by
the management software setting the bits within the SIO register in an appropriate manner. Refer to IEEE Std
802.2u and MII data sheets for the appropriate protocol requirements.
10-Mbit/s and 10-/100-Mbit/s MAC interface
receive control
Data received from the PHYs is interpreted and assembled into the TNETX3270 buffer memory. Interpretation
involves detection and removal of the preamble, extraction of the address and frame length, extraction of the
IEEE Std 802.1Q header (if present), and data handling and CRC. A jabber-detection timer also is included to
detect frames that exceed maximum length being received on the network.
giant (long) frames
The maxlen bit within each port’s Portxcontrol register controls the maximum received frame size on that port.
If maxlen = 0, the maximum received frame length Is 1535 bytes if no VLAN header is inserted, or 1531 bytes
if a VLAN header is inserted. (When stored within the switch, a frame never can be longer than 1535 bytes.)
If maxlen = 1, the maximum received frame length is 1518 bytes, as specified by the IEEE Std 802.3. This
is the maximum length on the wire. If a VLAN header is inserted into a 1518-byte frame within the MAC,
the frame is stored as a 1522-byte frame within the switch.
All received frames longer than the maximum size are discarded by the switch.
The long option bit in StatControl indicates how the statistics for long frames should be recorded.
short frames
All received frames shorter than 64 bytes are discarded upon reception and are not stored in memory or
transmitted.