Timing requirements see Figure | Texas Instruments TNETX3270

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

10-/100-Mbit/stransmit ports (24, 25, and 26)

timing requirements (see Figure 15)

NO.			MIN	MAX	UNIT

1	tc(MxxTCLK)	Cycle time, MxxTCLK	25	25	ns
2	tw(MxxTCLKL)	Pulse duration, MxxTCLK low			ns
3	tw(MxxTCLKH)	Pulse duration, MxxTCLK high	14		ns

operating characteristics over recommended operating conditions (see Note 8 and Figure 15)

NO.

PARAMETER

MIN

MAX

UNIT

4²

t

d(MxxTXD)

Delay time, from MxxTCLK↑ to MxxTXD3±MxxTXD0 valid

0

25

ns

4²

t

d(MxxTXEN)

Delay time, from MxxTCLK↑ to MxxTXEN valid

0

25

ns

4²

t

d(MxxTXER)

Delay time, from MxxTCLK↑ to MxxTXER valid

0

25

ns

² xx = ports 24, 25, and 26

NOTE 8:

Both MxxCRS and MxxCOL are driven asynchronously by the PHY. MxxTXD3±MxxTXD0 is driven by the reconciliation sublayer

synchronous to the MxxTCLK. MxxTXEN is asserted and deasserted by the reconciliation sublayer synchronous to the MxxTCLK rising

edge. MxxTXER is driven synchronous to the rising edge of MxxTCLK.

1

4

2

3

MxxTCLK (input)

MxxTXD3±MxxTXD0

MxxTXEN

MxxTXER

(outputs)

Figure 15. 10-/100-Mbit/s Transmit Ports

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

55

Image 55

Texas Instruments TNETX3270 specifications Timing requirements see Figure, 10-/100-Mbit/stransmit ports 24, 25

Contents

With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch Description With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Contents ThunderSWITCH 24/3 ETHERNET PGV Package TOP View  24/3 ThunderSWITCH Terminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³ 10-/100-Mbit/s MAC interface ports 24±26 ² Terminal Functions Dras Sdram interfaceDras Dcas Dclk Host DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QID VLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QID Findcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCI Short frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long frames Adaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit control Uplink pretagging Receive versus transmit priority Source Port Source-Port Pretag Encoding TAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomes LED interface Jtag interfaceJtag Instruction Opcodes Highz instruction Multi-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp test TNETX3270 TNETE2008 Terminal Mbit/s Interface Connections M03COL Port CLK Sync TXD3M03TXD M04TXD M06TXD Connecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±26 Duplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270 Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication Initialization Vlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroring Flow control Port trunking/load sharing Ieee Std 802.3 flow control Collision-based flow control Pause frame reception Internal wrap test PHY TNETX3270 Duplex wrap test Copy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit Timing requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see Figure Sdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dclk DIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom ² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid TtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑ Mechanical Data Important Notice