Texas Instruments TNETX3270 specification

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

LED interface

operating characteristics over recommended operating conditions (see Figure 22)

NO.			PARAMETER				MIN	MAX	UNIT

1	tc(LEDCLK)	Cycle time, LEDCLK						96	ns
2	tw(LEDCLKH)	Pulse duration, LEDCLK high					38	58	ns
3		Number of LEDCLK pulses in burst						48²
4	tc(BURST)	Cycle time, LEDCLK burst						62	ms
5	td(LEDCLK)	Delay time, from		to LEDCLK↑				12	μs
5	td(LEDCLK)	Delay time, from	LEDDATA	to LEDCLK↑				12	μs
6	td(LEDDATA)	Delay time, from LEDCLK↑ to				(1st LED invalid)		84	μs
6	td(LEDDATA)	Delay time, from LEDCLK↑ to			LEDDATA	(1st LED invalid)		84	μs

² During hard reset, LEDCLK runs continuously.

5

LEDCLK (output)

LEDDATA (input/output)

1

6

2

First LED

4

3

Second LED

Last LED

First LED

Figure 22. LED

62	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 62

Texas Instruments TNETX3270 specifications TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid

Contents

TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Description ThunderSWITCH 24/3 ETHERNET Contents PGV Package TOP View ThunderSWITCH  24/3 Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name Resistor Terminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ² Dclk Sdram interfaceDras Dcas Dras Host DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QID VLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QID Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8 Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRC Giant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short frames Transmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacing Receive versus transmit priority Uplink pretagging Source-Port Pretag Encoding Source Port Port 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load Outcomes Highz instruction Jtag interfaceJtag Instruction Opcodes LED interface Lamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED display Mbit/s Interface Connections TNETX3270 TNETE2008 Terminal M06TXD Port CLK Sync TXD3M03TXD M04TXD M03COL Connecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface Connections 10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal Function Initialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication Refresh Iale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDE Port trunking/load sharing Flow control Collision-based flow control Ieee Std 802.3 flow control Pause frame reception Internal wrap test Duplex wrap test PHY TNETX3270 Copy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit 10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25, Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras Dcas SDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAX TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuously ThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fall Mechanical Data Important Notice