TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions10-Mbit/s MAC multiplexed interface (ports 00–23) is multiplexed into three groups (TH0, TH1, and
TH2) of eight ports
TERMINAL
I/O
INTERNAL
DESCRIPTION
NAME NO.
I/O
RESISTOR
DESCRIPTION
TH0CLK
TH1CLK
TH2CLK
222
2
23 I Pullup Interface clock. Eight ports are supported on each interface and use this common 20-MHz
clock.
TH0COL
TH1COL
TH2COL
223
3
24 I Pulldown Interface collision sense. Assertion of THxCOL during half-duplex operation indicates
network collision on the current port. Additionally, during full-duplex operation, transmission
of new frames does not start if this terminal is asserted.
TH0CRS
TH1CRS
TH2CRS
224
5
25 I Pulldown Interface carrier sense. THxCRS indicates a frame carrier signal is being received on a
current port.
TH0LINK
TH1LINK
TH2LINK
232
13
32 I Pulldown
Interface link presence. THxLINK indicates the presence of the connection on a port.
– Low = no link
– High = link good
TH0RENEG
TH1RENEG
TH2RENEG
213
233
15 O None Interface renegotiate. A 1-0-1 sequence output on THxRENEG causes flow control and
half/full duplex for a port to be renegotiated with its companion physical-layer (PHY) device.
These THxRENEG terminals connect to IFFORCEHD on TNETE2008.
TH0RXD3
TH0RXD2
TH0RXD1
TH0RXD0
TH1RXD3
TH1RXD2
TH1RXD1
TH1RXD0
TH2RXD3
TH2RXD2
TH2RXD1
TH2RXD0
231
230
228
227
11
10
9
7
30
29
28
27
I Pullup
Interface receive data. The receive data nibble from the current port is synchronous to
THxCLK. When the THxRXDV signal is 1, the receive data terminals contain valid information.
THxRXD0 is the least significant bit and THxRXD3 is the most significant bit. These signals
also are used to report the channel state to the MAC.
TH0TXEN
TH1TXEN
TH2TXEN
219
240
21 O None Interface transmit enable. THxTXEN indicates valid transmit data on THxTXD.
TH0SYNC
TH1SYNC
TH2SYNC
221
1
22 I Pullup
Interface synchronize. THxSYNC is used to synchronize the port traffic between the
media-access controller (MAC) and PHY. When THxSYNC is a 1, the current MAC-to-PHY
path is the multiplexer interface TH0, and the PHY-to-MAC path is the multiplexer interface
TH2. THxSYNC is sampled by the MAC on the falling edge of THxCLK.
THx = TH0, TH1, and TH2
Internal resistors are provided to pull signals to known values. System designers should determine if additional pullups or pulldowns are required
in their system.