TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

Terminal Functions

10-Mbit/s MAC multiplexed interface (ports 00±23) is multiplexed into three groups (TH0, TH1, and TH2) of eight ports²

 

TERMINAL

 

I/O

INTERNAL

 

DESCRIPTION

 

NAME

NO.

RESISTOR³

 

 

 

 

 

 

 

 

TH0CLK

222

 

 

Interface clock. Eight ports are supported on each interface and use this common 20-MHz

 

TH1CLK

2

I

Pullup

 

clock.

 

 

 

 

TH2CLK

23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TH0COL

223

 

 

Interface collision sense. Assertion of THxCOL² during half-duplex operation indicates

 

TH1COL

3

I

Pulldown

network collision on the current port. Additionally, during full-duplex operation, transmission

 

TH2COL

24

 

 

of new frames does not start if this terminal is asserted.

 

 

 

 

 

 

 

 

 

 

 

TH0CRS

224

 

 

Interface carrier sense. THxCRS²

indicates a frame carrier signal is being received on a

 

TH1CRS

5

I

Pulldown

 

current port.

 

 

 

 

TH2CRS

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TH0LINK

232

 

 

Interface link presence. THxLINK²

indicates the presence of the connection on a port.

 

TH1LINK

13

I

Pulldown

± Low = no link

 

 

 

 

TH2LINK

32

 

 

± High = link good

 

 

 

 

 

 

 

 

 

 

 

 

 

 

213

 

 

Interface renegotiate. A 1-0-1 sequence output on

 

causes flow control and

 

TH0RENEG

 

 

 

THxRENEG

 

TH1RENEG

233

O

None

half/full duplex for a port to be renegotiated with its companion physical-layer (PHY) device.

 

TH2RENEG

15

 

 

These THxRENEG terminals connect to IFFORCEHD on TNETE2008.

 

 

 

 

 

 

 

 

 

 

TH0RXD3

231

 

 

 

 

 

 

 

TH0RXD2

230

 

 

 

 

 

 

 

TH0RXD1

228

 

 

 

 

 

 

 

TH0RXD0

227

 

 

 

 

 

 

 

TH1RXD3

11

 

 

Interface receive data. The receive data nibble from the current port is synchronous to

 

TH1RXD2

10

I

Pullup

THxCLK. When the THxRXDV signal is 1, the receive data terminals contain valid information.

 

TH1RXD1

9

THxRXD0 is the least significant bit and THxRXD3 is the most significant bit. These signals

 

 

 

 

TH1RXD0

7

 

 

also are used to report the channel state to the MAC.

 

TH2RXD3

30

 

 

 

 

 

 

 

TH2RXD2

29

 

 

 

 

 

 

 

TH2RXD1

28

 

 

 

 

 

 

 

TH2RXD0

27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TH0TXEN

219

 

 

 

 

 

 

 

TH1TXEN

240

O

None

Interface transmit enable. THxTXEN indicates valid transmit data on THxTXD.

 

TH2TXEN

21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TH0SYNC

221

 

 

Interface synchronize. THxSYNC

is used to synchronize the port traffic between the

 

 

 

media-access controller (MAC) and PHY. When THxSYNC is a 1, the current MAC-to-PHY

 

TH1SYNC

1

I

Pullup

 

path is the multiplexer interface TH0, and the PHY-to-MAC path is the multiplexer interface

 

TH2SYNC

22

 

 

 

 

 

TH2. THxSYNC is sampled by the MAC on the falling edge of THxCLK.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

² THx = TH0, TH1, and TH2

³Internal resistors are provided to pull signals to known values. System designers should determine if additional pullups or pulldowns are required in their system.

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Texas Instruments TNETX3270 specifications Terminal Internal Description Name RESISTOR³