Mbit/s Interface Connections | Texas Instruments TNETX3270 guide

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

10-/100-Mbit/s MAC interfaces (ports 24±26)

Unlike the 10-Mbit/s ports, each 10-/100-Mbit/s port has a dedicated set of signals to interface to its PHY. Table 12 shows how a TNETE2101 10-/100-Mbit/s PHY would be connected to one of the 10-/100-Mbit/s ports of TNETX3270.

Table 12. 10-/100-Mbit/s Interface Connections

	SWITCH			TNETE2101
TERMINAL				TERMINAL

MxxTCLK			←	MTCLK

MxxTXD3			→	MTXD3

MxxTXD2			→	MTXD2

MxxTXD1			→	MTXD1

MxxTXD0			→	MTXD0

MxxTXEN			→	MTXEN

MxxTXER			→	MTXER

	MxxCOL		←	MCOL

	MxxCRS		←	MCRS

MxxRCLK			←	MRCLK

MxxRXD3			←	MRXD3

MxxRXD2			←	MRXD2

MxxRXD1			←	MRXD1

MxxRXD0			←	MRXD0

MxxRXDV			←	MRXDV

MxxRXER			←	MRXER

	MxxLINK		←	SLINK

	MDCLK		→	MDCLK

	MDIO		↔		MDIO

			→
	MRESET		→		MRST

Where xx = 24, 25, or 26, y = 0±3

Other differences from the 10-Mbit/s ports are noted in following paragraphs.

10-/100-Mbit/s port configuration

The 100-Mbit/s ports (24±26) can negotiate with the PHY (speed and duplex) at power-up via the EEPROM contents using the MxxFORCE10 and MxxFORCEHD terminals, respectively.

Each of these terminals (per port):

DHas an integral 50-μA current-source pullup resistor. The system designer must decide if this is sufficient to achieve a logic-1 level in a timely manner or if an external supplementary resistor is required.

DHas a strong open-drain pulldown transistor, which is enabled by setting to 1 the appropriate bit in the Portxcontrol register.

DIs connected (via synchronization logic) to the appropriate bit in the Portxstatus register. These bits directly control the configuration of the ports.

34	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 34

Texas Instruments TNETX3270 specifications 10-/100-Mbit/s MAC interfaces ports 24±26, Mbit/s Interface Connections

Contents

TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Description ThunderSWITCH 24/3 ETHERNET Contents PGV Package TOP View ThunderSWITCH  24/3 Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name Resistor Terminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ² Dclk Sdram interfaceDras Dcas Dras Host DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QID VLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QID Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8 Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRC Giant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short frames Transmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacing Receive versus transmit priority Uplink pretagging Source-Port Pretag Encoding Source Port TAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load Outcomes Highz instruction Jtag interfaceJtag Instruction Opcodes LED interface Lamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED display Mbit/s Interface Connections TNETX3270 TNETE2008 Terminal M06TXD Port CLK Sync TXD3M03TXD M04TXD M03COL Connecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface Connections Duplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal Function Initialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication Refresh Vlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDE Port trunking/load sharing Flow control Collision-based flow control Ieee Std 802.3 flow control Pause frame reception Internal wrap test Duplex wrap test PHY TNETX3270 Copy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit Timing requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25, Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras Dcas DIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAX TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuously ThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fall Mechanical Data Important Notice