TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999
DIO/DMA read cycle
timing requirements (see Figure 19)
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| MIN MAX | UNIT |
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1 | tw(SCSL) | Pulse duration, |
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| low |
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SCS |
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2 | tw(SCSH) | Pulse duration, |
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| high | 14 | ns | |||||||
SCS | ||||||||||||||||
3 | tsu(SRNW) | Setup time, |
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| high before |
| ↓ | 0 | ns | ||||||
SRNW | SCS | |||||||||||||||
4 | tsu(SAD) | Setup time, SAD1±SAD0 and |
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| valid before |
| ↓ | 0 | ns | ||||||
SDMA | SCS | |||||||||||||||
operating characteristics over recommended operating conditions (see Figure 19)
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| PARAMETER | MIN | MAX | UNIT | ||||||
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5 | tw(SRDYH) | Pulse duration, |
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| high |
| 12 | ns | ||||||||||
SRDY |
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6 | td(SRNW) | Delay time, from |
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| ↓ to |
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| ↓ | 0 |
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SRDY |
| SRNW |
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7 | td(SAD) | Delay time, from |
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| ↓ to SAD1±SAD0 and |
| invalid | 0 |
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SRDY | SDMA |
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8 | td(SCS) | Delay time, from |
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| ↓ to |
| ↑ | 0 |
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SRDY | SCS |
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9 | td(SRDY) | Delay time, from SDATA7±SDATA0 to |
| ↓ | 0 |
| ns | |||||||||||||
SRDY |
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10 | td(SRDYZH) | Delay time, from |
| ↓ to |
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| ↑ | 0 |
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SCS | SRDY |
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11 | t | Delay time, from |
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| ↓ to |
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| ↓² | 0 |
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SCS | SRDY |
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| d(SRDY)2 |
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12 | td(SDATAZ) | Delay time, from |
| ↑ to SDATA7±SDATA0 Z state | 0 | 6 | ns | |||||||||||||
SCS | ||||||||||||||||||||
13 | td(SRDY)3 | Delay time, from |
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| ↑ to |
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| ↑ | 0 | 12 | ns | |||||||||
SCS | SRDY | |||||||||||||||||||
²When the switch is performing certain internal operations (e.g., EEPROM load), there may be a considerable delay (approximately 25±100 ms) between SCS being asserted and SRDY being asserted.
| 1 |
| 2 |
4 | 11 |
| 13 |
3 | 10 | 8 | 12 |
SCS |
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(input) |
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| 6 |
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SRNW |
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(input) |
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| 7 |
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SAD1±SAD0,
SDMA (inputs)
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SDATA7± | Z | Z |
SDATA0 |
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(outputs) |
| 5 |
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SRDY | Z |
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(output) |
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Figure 19. DIO/DMA Read Cycle
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 | 59 |
