Port CLK Sync TXD3, M03TXD M04TXD | Texas Instruments TNETX3270

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

	PORT	0	1	2	3	4	5	6	7	0	1
	CLK
	SYNC
	TXD3-	M00TXD	M01TXD	M02TXD	M03TXD	M04TXD	M05TXD	M06TXD	M07TXD	M00TXD	M01TXD
	TXD0	M00TXD	M01TXD	M02TXD	M03TXD	M04TXD	M05TXD	M06TXD	M07TXD	M00TXD	M01TXD
	TXD0
	TXEN	M00TXEN	M01TXEN	M02TXEN	M03TXEN	M04TXEN M05TXEN M06TXEN M07TXEN M00TXEN M01TXEN
	FORCEHD	M00FHD	M01FHD	M02FHD	M03FHD	M04FHD M05FHD M06FHD M07FHD M00FHD M01FHD
	COL	M02COL	M03COL	M04COL	M05COL	M06COL M07COL M00COL M01COL M02COL M03COL
	CRS	M02CRS	M03CRS	M04CRS	M05CRS	M06CRS M07CRS M00CRS M01CRS M02CRS M03CRS
	LINK	M02LINK	M03LINK	M04LINK	M05LINK	M06LINK	M07LINK	M00LINK	M01LINK	M02LINK	M03LINK
	RXD3-	M02RXD	M03RXD	M04RXD	M05RXD	M06RXD	M07RXD	M00RXD	M01RXD	M02RXD	M03RXD
	RXD0	M02RXD	M03RXD	M04RXD	M05RXD	M06RXD	M07RXD	M00RXD	M01RXD	M02RXD	M03RXD
	RXD0
	RXDV	M02RXDV M03RXDV M04RXDV M05RXDV M06RXDV M07RXDV M00RXDV M01RXDV M02RXDV M03RXDV

Figure 6. 10-Mbit/s Interface-Port Signal Timing

32	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 32

Texas Instruments TNETX3270 Port CLK Sync TXD3, M03TXD M04TXD, M06TXD, M06COL M07COL M00COL M01COL M02COL M03COL, Crs

Contents

TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Description ThunderSWITCH 24/3 ETHERNET Contents PGV Package TOP View ThunderSWITCH  24/3 Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name Resistor Terminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ² Sdram interface Dras DcasDclk Dras Host DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN1QID VLAN0QID VLAN3QID VLAN2QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QID VLAN17QID VLAN16QID VLAN19QID VLAN18QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QID Intenable TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFFFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8 Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port Vlan ID FCSTpid TCI CRC MII serial management interface PHY management Mbit/s and 10-/100-Mbit/s MAC interface receive controlGiant long frames Short frames Receive filtering of frames Data transmissionTransmit control Adaptive performance optimization APO transmit pacing Receive versus transmit priority Uplink pretagging Source-Port Pretag Encoding Source Port Port 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Summary of Eeprom Load Outcomes Jtag interface Jtag Instruction OpcodesHighz instruction LED interface Hardware configurations LED Status Bit Definitions and Shift OrderLamp test Multi-LED display Mbit/s Interface Connections TNETX3270 TNETE2008 Terminal Port CLK Sync TXD3 M03TXD M04TXDM06TXD M03COL Connecting to TNETE2008 PHY² 10-/100-Mbit/s port configuration Switch TNETE2101 Terminal10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections 10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Sdram interface TNETX3270 Terminal Interface to SDRAMs Sdram Terminals Not Driven by the TNETX3270Terminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal Function TNETX3270 State Terminal During Reset SDRAM-type and quantity indicationInitialization Refresh Iale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDE Port trunking/load sharing Flow control Collision-based flow control Ieee Std 802.3 flow control Pause frame reception Internal wrap test Duplex wrap test PHY TNETX3270 Copy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit 10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25, Sdram command to command see Figure TdDA Delay time, from Dclk ↑ to DA Invalid Sdram subcycleDclk Dras Dcas SDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAX TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuously Power-up Oscin and Reset Timing requirements see Figure TsuRESET Setup time Low before Oscin ↑ThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fall Mechanical Data Important Notice