Mechanical Data | Texas Instruments TNETX3270 guide

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

MECHANICAL DATA

PGV (S-PQFP-G240)

PLASTIC QUAD FLATPACK (DIE±DOWN)

180		121
181		Heat Slug	120
		Heat Slug
			0,27	0,08	M
			0,17	0,08	M
			0,17
			0,50
					0,16 NOM
240			61
1		60		Gage Plane
29,50 TYP
32,20	SQ		0,25
31,80	SQ		0,25 MIN		0°± 7°
31,80
34,80			0,75
34,80			0,75
34,40 SQ			0,50
3,80 TYP
			Seating Plane
4,20 MAX			0,08
				4040247/ A 03/95

NOTES: A. All linear dimensions are in millimeters.

B.This drawing is subject to change without notice.

C.Thermally enhanced molded plastic package with a heat slug (HSL)

64	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 64

Texas Instruments TNETX3270 specifications Mechanical Data

Contents

TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Description ThunderSWITCH 24/3 ETHERNET Contents PGV Package TOP View ThunderSWITCH  24/3 Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name Resistor Terminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ² Sdram interface Dras DcasDclk Dras Host DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN1QID VLAN0QID VLAN3QID VLAN2QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QID VLAN17QID VLAN16QID VLAN19QID VLAN18QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QID Intenable TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFFFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8 Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port Vlan ID FCSTpid TCI CRC MII serial management interface PHY management Mbit/s and 10-/100-Mbit/s MAC interface receive controlGiant long frames Short frames Receive filtering of frames Data transmissionTransmit control Adaptive performance optimization APO transmit pacing Receive versus transmit priority Uplink pretagging Source-Port Pretag Encoding Source Port TAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Summary of Eeprom Load Outcomes Jtag interface Jtag Instruction OpcodesHighz instruction LED interface Hardware configurations LED Status Bit Definitions and Shift OrderLamp test Multi-LED display Mbit/s Interface Connections TNETX3270 TNETE2008 Terminal Port CLK Sync TXD3 M03TXD M04TXDM06TXD M03COL Connecting to TNETE2008 PHY² 10-/100-Mbit/s port configuration Switch TNETE2101 Terminal10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections Duplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram interface TNETX3270 Terminal Interface to SDRAMs Sdram Terminals Not Driven by the TNETX3270Terminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal Function TNETX3270 State Terminal During Reset SDRAM-type and quantity indicationInitialization Refresh Vlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDE Port trunking/load sharing Flow control Collision-based flow control Ieee Std 802.3 flow control Pause frame reception Internal wrap test Duplex wrap test PHY TNETX3270 Copy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit Timing requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25, Sdram command to command see Figure TdDA Delay time, from Dclk ↑ to DA Invalid Sdram subcycleDclk Dras Dcas DIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAX TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuously Power-up Oscin and Reset Timing requirements see Figure TsuRESET Setup time Low before Oscin ↑ThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fall Mechanical Data Important Notice