Sdram subcycle, Dclk, Dras Dcas | Texas Instruments TNETX3270

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

SDRAM subcycle

operating characteristics over recommended operating conditions (see Figure 17)

NO.

PARAMETER

MIN

MAX

UNIT

1

tc(DCLK)

Cycle time, DCLK

12

12

ns

2

tw(DCLKL)

Pulse duration, DCLK low

5

ns

3

tw(DCLKH)

Pulse duration, DCLK high

5

ns

4

td(DCLK)

Delay time, from DA,

and

valid to DCLK↑

4

ns

DRAS,

DCAS,

DW

5

td(DA)

Delay time, from DCLK↑ to DA,

and

invalid

2

ns

DRAS,

DCAS,

DW

6

ten(DDW)

Enable time, from DCLK↑ to before DD31±DD00 driven (write cycle)

0

ns

7

ten(DDR)

Enable time, from DCLK↑ to before DD31±DD00 driven (read cycle)

0

ns

8

tdis(DDW)

Disable time, from DCLK↑ to after DD31±DD00 (after final write cycle) to Z state

10

ns

9

tdis(DDR)

Disable time, from DCLK↑ to after DD31±DD00 (after final read cycle) to Z state

11

ns

10

td(DDW)1

Delay time, from DD valid to DCLK↑ (write cycle)

4

ns

11

td(DDW)2

Delay time, from DCLK↑ to DD31±DD00 Z state (write cycle)

2

ns

12

td(DDR)1

Delay time, from DCLK↑ to DD31±DD00 valid (read cycle)

10

ns

13

td(DDR)2

Delay time, from DCLK↑ to DD31±DD00 invalid (read cycle)

0

ns

tt

Transition time, rise and fall, all signals

1

4

ns

		1
	2	3
DCLK
(output)
	4	5
DA13±DA00
DRAS
DCAS
DW	6	8
(outputs)	6	8
DD31±DD00	10	11
DD31±DD00	Z
(during writes)	Z
(during writes)
(output)
	12	9
	7	13
DD31±DD00	Z
(during reads)	Z
(during reads)
(input)

Figure 17. SDRAM Subcycle

Z

Z

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

57

Image 57

Texas Instruments TNETX3270 specifications Sdram subcycle, TdDA Delay time, from Dclk ↑ to DA Invalid, Dras Dcas

Contents

With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch Description With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Contents ThunderSWITCH 24/3 ETHERNET PGV Package TOP View  24/3 ThunderSWITCH Terminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³ 10-/100-Mbit/s MAC interface ports 24±26 ² Terminal Functions Dras Dcas Sdram interfaceDclk Dras Host DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN3QID VLAN2QID VLAN1QID VLAN0QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QID VLAN19QID VLAN18QID VLAN17QID VLAN16QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QID TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF IntenableFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8 State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port FCS Vlan IDTpid TCI CRC Mbit/s and 10-/100-Mbit/s MAC interface receive control MII serial management interface PHY managementGiant long frames Short frames Data transmission Receive filtering of framesTransmit control Adaptive performance optimization APO transmit pacing Uplink pretagging Receive versus transmit priority Source Port Source-Port Pretag Encoding Received Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Summary of Eeprom Load Outcomes Jtag Instruction Opcodes Jtag interfaceHighz instruction LED interface LED Status Bit Definitions and Shift Order Hardware configurationsLamp test Multi-LED display TNETX3270 TNETE2008 Terminal Mbit/s Interface Connections M03TXD M04TXD Port CLK Sync TXD3M06TXD M03COL Connecting to TNETE2008 PHY² Switch TNETE2101 Terminal 10-/100-Mbit/s port configuration10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections Speed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram Terminals Not Driven by the TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsTerminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal Function SDRAM-type and quantity indication TNETX3270 State Terminal During ResetInitialization Refresh Frame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroring Flow control Port trunking/load sharing Ieee Std 802.3 flow control Collision-based flow control Pause frame reception Internal wrap test PHY TNETX3270 Duplex wrap test Copy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit 10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see Figure Sdram command to command see Figure Sdram subcycle TdDA Delay time, from Dclk ↑ to DA InvalidDclk Dras Dcas DIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom ² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid TsuRESET Setup time Low before Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fall Mechanical Data Important Notice