Texas Instruments TNETX3270 SDRAM interface

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SDRAM interface

The SDRAM interface observes two types of timing:

Multicycle timings between commands

Subcycle timings between signals and DCLK

Figure 16 illustrates the SDRAM interfaces signal timing in which each type of SDRAM command and its

interrelated timings are shown. It is not intended to be representative of any particular receive or transmit buffer

operation.

SDRAM command to command (see Figure 16)

SYMBOL PARAMETER MIN MAX UNIT

tRSA MRS to ACTV or REFR 24 ns

tRC Row cycle time (ACTV to REFR to next ACTV or REFR) 120 ns

tRAS Row active time (ACTV to DCAB) 72 ns

tRP Row recharge time (DCAB to ACTV, REFR, or MRS) 36 ns

tRCD Row to column delay (ACTV to READ or WRT) 36 ns

tAC3 Column access time [READ (CAS) latency] (READ to data sample) 36 ns

nCCD Column address to column address (WRT to next READ or WRT, or READ to next READ) 24 ns

nCWL Last data or write to new column address (WRT to next READ or WRT) 24 ns

tRWD Read to write delay (READ to next WRT) 60 ns

tWR Write recovery time (WRT to DCAB) 24 ns

DCLK

tRC tRP

tRWD tWR

nCWL

nCCD

tRCD

tRAS

tRSA tAC3 tAC3

DRAS

DCAS

DW

DD31–DD00

DA13–DA00

REGISTER

SETTINGS

BUFFOP READ1 WRITE READ2

MODE ROW READ1 WRITE READ2 XXXX

DA10=0 DA10=0 DA10=1DA10=0

NOOP NOOP ACTV READ READ DCAB REFRNOOP NOOP NOOPNOOP NOOP NOOP WRT NOOP NOOPMRS

Figure 16. SDRAM Command to Command

Contents

Main TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS description TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B NOVEMBER 1997 REVISED APRIL 1999 PGV PACKAGE (TOP VIEW) ThunderSWITCH 24/3 ETHERNET SWITCH PRODUCT PREVIEW Figure 1. TNETX3270 Interface Block Diagram Page TNETX3270 10-/100-Mbit/s MAC interface (ports 2426) 10-/100-Mbit/s MAC interface (ports 2426) (continued) SDRAM interface WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS host DIO interface serial MII management PHY interface EEPROM interface LED interface JTAG interface miscellaneous power interface summary of signal terminals by signal group function DIO register groups Table 1. Internal Register and Statistics Memory Map Table 2. Detailed DIO Register Map Page Page Page interface description receiving/transmitting management frames state of DIO signals during hardware reset network management port Page Page receive control giant (long) frames short frames receive filtering of frames data transmission transmit control adaptive performance optimization (APO) (transmit pacing) interframe gap enforcement ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS receive versus transmit priority uplink pretagging Table 5. Source-Port Pretag Encoding Page TNETX3270 interaction of EEPROM load with the SIO register summary of EEPROM load outcomes compatibility with future device revisions HIGHZ instruction lamp test multi-LED display hardware configurations Page TNETX3270 Figure 6. 10-Mbit/s Interface-Port Signal Timing Figure 7. Connecting to TNETE2008 PHY 10-/100-Mbit/s port configuration 10-/100-Mbit/s port configuration (continued) 10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch SDRAM interface (continued) Table 15. TNETX3270 Terminal Interface to SDRAMs SDRAM-type and quantity indication initialization refresh 39 frame routing txacc Figure 8. VLAN Overview Transmit rxacc IEEE Std 802.1Q headers reception IEEE Std 802.1Q headers transmission address maintenance spanning-tree support aging algorithms frame-routing determination Unkmem Figure 9. Frame-Routing Algorithm interrupt UnkVLAN Figure 9. Frame-Routing Algorithm (Continued) new chng secvio Port Trunking/Load Sharing port mirroring port trunking/load sharing collision-based flow control IEEE Std 802.3 flow control Page internal wrap test duplex wrap test Page absolute maximum ratings over operating junction temperature range (unless otherwise noted) recommended operating conditions electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MEASUREMENT INFORMATION test measurement 10-Mbit/s interface (ports 0023) timing requirements (see Notes 3 through 6 and Figure 13) Figure 13. 10-Mbit/s Interface (Ports 0023) 10-/100-Mbit/s MAC interface Figure 14. 10-/100-Mbit/s Receive Ports 10-/100-Mbit/s timing requirements (see Note 7 and Figure 14) 10-/100-Mbit/s timing requirements (see Figure 15) operating characteristics over recommended operating conditions (see Note 8 and Figure 15) Figure 15. 10-/100-Mbit/s Transmit Ports SDRAM interface SDRAM subcycle operating characteristics over recommended operating conditions (see Figure 17) Figure 17. SDRAM Subcycle DIO/DMA interface Figure 18. DIO/DMA Write Cycle timing requirements (see Figure 18) operating characteristics over recommended operating conditions (see Figure 18) DIO/DMA read cycle timing requirements (see Figure 19) Figure 19. DIO/DMA Read Cycle operating characteristics over recommended operating conditions (see Figure 19) serial MII management interface timing requirements (see Figure 20) operating characteristics over recommended operating conditions (see Figure 20) Figure 20. Serial MII Management Read/Write Cycle EEPROM interface operating characteristics over recommended operating conditions (see Figure 21) Figure 21. EEPROM LED interface operating characteristics over recommended operating conditions (see Figure 22) Figure 22. LED power-up OSCIN and RESET timing requirements (see Figure 23) Figure 23. Power-Up OSCIN and RESET MECHANICAL DATA PGV (S-PQFP-G240) PLASTIC QUAD FLATPACK (DIEDOWN)