Sdram command to command see Figure | Texas Instruments TNETX3270

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

SDRAM interface

The SDRAM interface observes two types of timing:

DMulticycle timings between commands

DSubcycle timings between signals and DCLK

Figure 16 illustrates the SDRAM interfaces signal timing in which each type of SDRAM command and its interrelated timings are shown. It is not intended to be representative of any particular receive or transmit buffer operation.

SDRAM command to command (see Figure 16)

SYMBOL				PARAMETER					MIN	MAX UNIT
tRSA	MRS to ACTV or REFR								24	ns
tRC	Row cycle time (ACTV to REFR to next ACTV or REFR)								120	ns
tRAS	Row active time (ACTV to DCAB)								72	ns
tRP	Row recharge time (DCAB to ACTV, REFR, or MRS)								36	ns
tRCD	Row to column delay (ACTV to READ or WRT)								36	ns
tAC3	Column access time [READ (CAS) latency] (READ to data sample)								36	ns
nCCD	Column address to column address (WRT to next READ or WRT, or READ to next READ)								24	ns
nCWL	Last data or write to new column address (WRT to next READ or WRT)								24	ns
tRWD	Read to write delay (READ to next WRT)								60	ns
tWR	Write recovery time (WRT to DCAB)								24
						tRC			tRP
					tRAS				tRP
						tRWD		tWR
							nCWL
		tRSA	tRCD		tAC3		nCCD		tAC3
DCLK
		MRS	ACTV	NOOP	NOOP	NOOP	WRT		DCAB	NOOP
	NOOP	NOOP	NOOP		READ	NOOP	NOOP	READ	NOOP	REFR
DRAS
DCAS
DW
DD31±DD00			BUFFOP			READ1	WRITE			READ2
DD31±DD00			BUFFOP			READ1	WRITE
DA13±DA00		MODE	ROW		READ1		WRITE	READ2	XXXX
REGISTER					DA10=0		DA10=0	DA10=0	DA10=1
SETTINGS

Figure 16. SDRAM Command to Command

56	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 56

Texas Instruments TNETX3270 specifications Sdram command to command see Figure

Contents

TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Description ThunderSWITCH 24/3 ETHERNET Contents PGV Package TOP View ThunderSWITCH  24/3 Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name Resistor Terminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ² Sdram interface Dras DcasDclk Dras Host DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN1QID VLAN0QID VLAN3QID VLAN2QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QID VLAN17QID VLAN16QID VLAN19QID VLAN18QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QID Intenable TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFFFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8 Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port Vlan ID FCSTpid TCI CRC MII serial management interface PHY management Mbit/s and 10-/100-Mbit/s MAC interface receive controlGiant long frames Short frames Receive filtering of frames Data transmissionTransmit control Adaptive performance optimization APO transmit pacing Receive versus transmit priority Uplink pretagging Source-Port Pretag Encoding Source Port Port 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Summary of Eeprom Load Outcomes Jtag interface Jtag Instruction OpcodesHighz instruction LED interface Hardware configurations LED Status Bit Definitions and Shift OrderLamp test Multi-LED display Mbit/s Interface Connections TNETX3270 TNETE2008 Terminal Port CLK Sync TXD3 M03TXD M04TXDM06TXD M03COL Connecting to TNETE2008 PHY² 10-/100-Mbit/s port configuration Switch TNETE2101 Terminal10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections 10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Sdram interface TNETX3270 Terminal Interface to SDRAMs Sdram Terminals Not Driven by the TNETX3270Terminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal Function TNETX3270 State Terminal During Reset SDRAM-type and quantity indicationInitialization Refresh Iale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDE Port trunking/load sharing Flow control Collision-based flow control Ieee Std 802.3 flow control Pause frame reception Internal wrap test Duplex wrap test PHY TNETX3270 Copy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit 10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25, Sdram command to command see Figure TdDA Delay time, from Dclk ↑ to DA Invalid Sdram subcycleDclk Dras Dcas SDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAX TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuously Power-up Oscin and Reset Timing requirements see Figure TsuRESET Setup time Low before Oscin ↑ThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fall Mechanical Data Important Notice