DIO register groups, Vlan | Texas Instruments TNETX3270 specs

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

DIO register groups

Table 1. Internal Register and Statistics Memory Map

	LOADABLE	LOADABLE	DIO
REGISTERS	USING 24C02	USING 24C08	ADDRESS
	EEPROM?	EEPROM?	RANGE

Port configuration	Yes	Yes	0x0000:0x002F

Spanning tree	Yes	Yes	0x0030:0x007F

Trunking	Yes	Yes	0x0080:0x0088

VLAN	No	Yes	0x0089:0x03FF

Port status	No	No	0x0400:0x043F

Address configuration	No	No	0x0440:0x08FF

Port statistics	No	No	0x0900:0xFFFF

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Texas Instruments TNETX3270 specifications DIO register groups, Internal Register and Statistics Memory Map, Vlan

Contents

With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch Description With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Contents ThunderSWITCH 24/3 ETHERNET PGV Package TOP View  24/3 ThunderSWITCH Terminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³ 10-/100-Mbit/s MAC interface ports 24±26 ² Terminal Functions Dras Dcas Sdram interfaceDclk Dras Host DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN3QID VLAN2QID VLAN1QID VLAN0QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QID VLAN19QID VLAN18QID VLAN17QID VLAN16QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QID TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF IntenableFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8 Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port FCS Vlan IDTpid TCI CRC Mbit/s and 10-/100-Mbit/s MAC interface receive control MII serial management interface PHY managementGiant long frames Short frames Data transmission Receive filtering of framesTransmit control Adaptive performance optimization APO transmit pacing Uplink pretagging Receive versus transmit priority Source Port Source-Port Pretag Encoding TAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Summary of Eeprom Load Outcomes Jtag Instruction Opcodes Jtag interfaceHighz instruction LED interface LED Status Bit Definitions and Shift Order Hardware configurationsLamp test Multi-LED display TNETX3270 TNETE2008 Terminal Mbit/s Interface Connections M03TXD M04TXD Port CLK Sync TXD3M06TXD M03COL Connecting to TNETE2008 PHY² Switch TNETE2101 Terminal 10-/100-Mbit/s port configuration10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections Duplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram Terminals Not Driven by the TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsTerminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal Function SDRAM-type and quantity indication TNETX3270 State Terminal During ResetInitialization Refresh Vlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroring Flow control Port trunking/load sharing Ieee Std 802.3 flow control Collision-based flow control Pause frame reception Internal wrap test PHY TNETX3270 Duplex wrap test Copy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit Timing requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see Figure Sdram command to command see Figure Sdram subcycle TdDA Delay time, from Dclk ↑ to DA InvalidDclk Dras Dcas DIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom ² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid TsuRESET Setup time Low before Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fall Mechanical Data Important Notice