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Texas Instruments TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS,

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TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCHWITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

receive versus transmit priority

The queue manager prioritizes receive and transmit traffic as follows:

Highest priority is given to frames that currently are being transmitted. This ensures that transmitting frames

do not underrun.

Next priority is given to frames that are received if the free-buffer stack is not empty. This ensures that

received frames are not dropped unless it is impossible to receive them.

Lowest priority is given to frames that are queued for transmission but have not yet started to transmit.

These frames are promoted to the highest priority only when there is spare capacity on the memory bus.

The NM port receives the lowest priority to prevent frame loss during busy periods.

The memory bus has enough bandwidth to support the two highest priorities. The untransmitted frame queues

grow when frames received on different ports require transmission on the same port(s) and when frames are

repeatedly received on ports that are at a higher speed than the ports on which they are transmitted. This is likely

to be exacerbated by the reception of multicast frames, which typically require transmission on several ports.

When the backlog grows to such an extent that the free buffer stack is nearly empty, flow control is initiated (if

it has been enabled) to limit further frame reception.

uplink pretagging

TNETX3270 can be incorporated into a switch where routing decisions can be made at a higher level. To

facilitate this, two forms of tags are provided on ports 24–26:

Source-port pretag on transmission

Port-routing-code pretag on reception

source-port pretag on transmission

Ports 24–26 provide the frame’s source-port-number pretag one cycle before MxxTXEN goes high (this tag is

ignored by an externally connected PHY). The 5-bit tag appears as an encoding on terminals MxxTXER and

MxxTXD3 to MxxTXD0 (most significant bit to least significant bit). This is shown in Figure 3 and Table 5.

MxxTCLK

MxxTXER Transmit ErrorTag MSB

MxxTXD3–MxxTXD0 Preamble and FrameTag LS 4 Bits

MxxTXEN

Figure 3. Source-Port Pretag

Contents

Main TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS description TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B NOVEMBER 1997 REVISED APRIL 1999 PGV PACKAGE (TOP VIEW) ThunderSWITCH 24/3 ETHERNET SWITCH PRODUCT PREVIEW Figure 1. TNETX3270 Interface Block Diagram Page TNETX3270 10-/100-Mbit/s MAC interface (ports 2426) 10-/100-Mbit/s MAC interface (ports 2426) (continued) SDRAM interface WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS host DIO interface serial MII management PHY interface EEPROM interface LED interface JTAG interface miscellaneous power interface summary of signal terminals by signal group function DIO register groups Table 1. Internal Register and Statistics Memory Map Table 2. Detailed DIO Register Map Page Page Page interface description receiving/transmitting management frames state of DIO signals during hardware reset network management port Page Page receive control giant (long) frames short frames receive filtering of frames data transmission transmit control adaptive performance optimization (APO) (transmit pacing) interframe gap enforcement ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS receive versus transmit priority uplink pretagging Table 5. Source-Port Pretag Encoding Page TNETX3270 interaction of EEPROM load with the SIO register summary of EEPROM load outcomes compatibility with future device revisions HIGHZ instruction lamp test multi-LED display hardware configurations Page TNETX3270 Figure 6. 10-Mbit/s Interface-Port Signal Timing Figure 7. Connecting to TNETE2008 PHY 10-/100-Mbit/s port configuration 10-/100-Mbit/s port configuration (continued) 10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch SDRAM interface (continued) Table 15. TNETX3270 Terminal Interface to SDRAMs SDRAM-type and quantity indication initialization refresh 39 frame routing txacc Figure 8. VLAN Overview Transmit rxacc IEEE Std 802.1Q headers reception IEEE Std 802.1Q headers transmission address maintenance spanning-tree support aging algorithms frame-routing determination Unkmem Figure 9. Frame-Routing Algorithm interrupt UnkVLAN Figure 9. Frame-Routing Algorithm (Continued) new chng secvio Port Trunking/Load Sharing port mirroring port trunking/load sharing collision-based flow control IEEE Std 802.3 flow control Page internal wrap test duplex wrap test Page absolute maximum ratings over operating junction temperature range (unless otherwise noted) recommended operating conditions electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MEASUREMENT INFORMATION test measurement 10-Mbit/s interface (ports 0023) timing requirements (see Notes 3 through 6 and Figure 13) Figure 13. 10-Mbit/s Interface (Ports 0023) 10-/100-Mbit/s MAC interface Figure 14. 10-/100-Mbit/s Receive Ports 10-/100-Mbit/s timing requirements (see Note 7 and Figure 14) 10-/100-Mbit/s timing requirements (see Figure 15) operating characteristics over recommended operating conditions (see Note 8 and Figure 15) Figure 15. 10-/100-Mbit/s Transmit Ports SDRAM interface SDRAM subcycle operating characteristics over recommended operating conditions (see Figure 17) Figure 17. SDRAM Subcycle DIO/DMA interface Figure 18. DIO/DMA Write Cycle timing requirements (see Figure 18) operating characteristics over recommended operating conditions (see Figure 18) DIO/DMA read cycle timing requirements (see Figure 19) Figure 19. DIO/DMA Read Cycle operating characteristics over recommended operating conditions (see Figure 19) serial MII management interface timing requirements (see Figure 20) operating characteristics over recommended operating conditions (see Figure 20) Figure 20. Serial MII Management Read/Write Cycle EEPROM interface operating characteristics over recommended operating conditions (see Figure 21) Figure 21. EEPROM LED interface operating characteristics over recommended operating conditions (see Figure 22) Figure 22. LED power-up OSCIN and RESET timing requirements (see Figure 23) Figure 23. Power-Up OSCIN and RESET MECHANICAL DATA PGV (S-PQFP-G240) PLASTIC QUAD FLATPACK (DIEDOWN)