Frame-Routing Algorithm | Texas Instruments TNETX3270 specification

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

Start

Key:

UnkVLAN

interrupt

Known

No

VLAN?

statistic

Unkmem

Yes

No

Source Port = 1 in.

VLANnports?

Yes

Yes

Destination

No

Address

Found?

Yes

Destination

No

Destination

Destination

No

Destination

No

Locked

is

is

is

Bit = 1?

Multicast?

Multicast?

Multicast?

No

Yes

Yes

Yes

Source

Port

Source Port

Source Port

Source

Port

Source Port

Yes

Blocked by

Blocked by

Blocked by

Blocked by

Blocked by

RxUniBlockPorts

RxMultiBlockPorts

RxMultiBlockPorts?

RxUniBlockPorts?

RxMultiBlockPorts or

and Dest.

and Dest.

UnkVLAN=0?

Nblck=0?

Yes

Nblck=0?

Yes

Yes

Yes

No

No

No

No

No

Port Routing

Port Routing

Port Routing

Port Routing

Port Routing

Code = Port Code

Code = Port Vector

Code =

Code =

Code =

From Records

From Records

UnkMultiPorts

UnkUniPorts

UnkVLANPort

Unknown

Unknown

Multicast

Unlcast

Set Port Routing

Destination

Destination

Code to 0

Destination

Yes

Include UplinkPort

AND Port Routing

in Port

Code With VLAN

Cuplink Bit

Routing Code

VLANnports Code

Set?

No

To C

To A

To B

(Continued)

(Continued)

(Continued)

Figure 9. Frame-Routing Algorithm

42	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 42

Texas Instruments TNETX3270 specifications Frame-Routing Algorithm

Contents

TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Description ThunderSWITCH 24/3 ETHERNET Contents PGV Package TOP View ThunderSWITCH  24/3 Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name Resistor Terminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ² Dclk Sdram interfaceDras Dcas Dras Host DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QID VLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QID Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8 State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRC Giant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short frames Transmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacing Receive versus transmit priority Uplink pretagging Source-Port Pretag Encoding Source Port Received Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load Outcomes Highz instruction Jtag interfaceJtag Instruction Opcodes LED interface Lamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED display Mbit/s Interface Connections TNETX3270 TNETE2008 Terminal M06TXD Port CLK Sync TXD3M03TXD M04TXD M03COL Connecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface Connections Speed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal Function Initialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication Refresh Frame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDE Port trunking/load sharing Flow control Collision-based flow control Ieee Std 802.3 flow control Pause frame reception Internal wrap test Duplex wrap test PHY TNETX3270 Copy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit 10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25, Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras Dcas DIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAX TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuously ThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fall Mechanical Data Important Notice