ThunderSWITCH,  24/3 | Texas Instruments TNETX3270 manual

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	JTAG	TRST
	JTAG	TMS
	Test Access	TMS
	Test Access	TCLK	TAP
	Port (TAP)	TCLK	TAP
	Port (TAP)	TDI
		TDI
		TDO

	DD31±DD0
DRAM	DA12±DA0
DRAM	DCLK	SDRAM	Queue
Port	DRAS	Controller	Manager
	DCAS
	DW
EEPROM	ECLK	EEPROM
Port	EDIO	Interface
Port	EDIO
SDATA7±SDATA0				Data
SAD1±SAD0			Network	Data
SAD1±SAD0			Network
	SRNW		Statistics	Path
CPU	SCS	CPU	Logic	Path
CPU	SRDY	CPU
Interface	SRDY	Interface
Interface	SDMA	Interface
	SDMA
	SINT
	STXRDY		Statistics
	SRXRDY		Storage
			MIB
LED	LEDDATA	LED	Address
Activity	LEDDATA	LED	Address
Activity	LEDCLK	Interface	Compare
Port	LEDCLK	Interface	Compare
Port
Serial	MDCLK
MII	MDIO	MII
Interface	MRESET
Miscellaneous	OSCIN
Functions	RESET

² xx is the port number that is being monitored.

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC) MII

Controller (MAC) MII

Controller (MAC) MII

MUX

MUX

MUX

TH0CLK

TH0TXD3±TH0TXD0

TH0TXEN

TH0COL

TH0CRS

TH0SYNC

TH0RXD3±TH0RXD0

TH0RXDV

TH0LINK TH0RENEG

TH1CLK

TH1TXD3±TH1TXD0

TH1TXEN

TH1COL

TH1CRS

TH1SYNC

TH1RXD3±TH1RXD0

TH1RXDV

TH1LINK TH1RENEG

TH2CLK

TH2TXD3±TH2TXD0

TH2TXEN

TH2COL

TH2CRS

TH2SYNC

TH2RXD3±TH2RXD0

TH2RXDV

TH2LINK TH2RENEG

MxxTCLK

MxxTXD3±MxxTXD0

MxxTXEN

MxxTXER

MxxCOL

MxxCRS

MxxRCLK

MxxRXD3±MxxRXD0

MxxRXDV

MxxRXER

MxxFORCE10

MxxFORCEHD

MxxLINK

Eight Ports (00±07)

10 Mbit/s

Eight Ports (08±15)

10 Mbit/s

Eight Ports (16±23)

10 Mbit/s

Three Ports (24±26)² 10/100 Mbit/s

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL

WITH 24 10-MBIT/S PORTS	ThunderSWITCH
AND 3	 24/3
10-/100-	ETHERNET
MBIT/SPORTS	TNETX3270 SWITCH

5

Figure 1. TNETX3270 Interface Block Diagram

1999

PRODUCT PREVIEW

Image 5

Texas Instruments TNETX3270 specifications ThunderSWITCH,  24/3

Contents

With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch Description With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Contents ThunderSWITCH 24/3 ETHERNET PGV Package TOP View  24/3 ThunderSWITCH Terminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³ 10-/100-Mbit/s MAC interface ports 24±26 ² Terminal Functions Dras Dcas Sdram interfaceDclk Dras Host DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN3QID VLAN2QID VLAN1QID VLAN0QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QID VLAN19QID VLAN18QID VLAN17QID VLAN16QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QID TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF IntenableFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8 Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port FCS Vlan IDTpid TCI CRC Mbit/s and 10-/100-Mbit/s MAC interface receive control MII serial management interface PHY managementGiant long frames Short frames Data transmission Receive filtering of framesTransmit control Adaptive performance optimization APO transmit pacing Uplink pretagging Receive versus transmit priority Source Port Source-Port Pretag Encoding Port 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Summary of Eeprom Load Outcomes Jtag Instruction Opcodes Jtag interfaceHighz instruction LED interface LED Status Bit Definitions and Shift Order Hardware configurationsLamp test Multi-LED display TNETX3270 TNETE2008 Terminal Mbit/s Interface Connections M03TXD M04TXD Port CLK Sync TXD3M06TXD M03COL Connecting to TNETE2008 PHY² Switch TNETE2101 Terminal 10-/100-Mbit/s port configuration10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections 10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Sdram Terminals Not Driven by the TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsTerminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal Function SDRAM-type and quantity indication TNETX3270 State Terminal During ResetInitialization Refresh Iale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroring Flow control Port trunking/load sharing Ieee Std 802.3 flow control Collision-based flow control Pause frame reception Internal wrap test PHY TNETX3270 Duplex wrap test Copy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit 10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see Figure Sdram command to command see Figure Sdram subcycle TdDA Delay time, from Dclk ↑ to DA InvalidDclk Dras Dcas SDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom ² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid TsuRESET Setup time Low before Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fall Mechanical Data Important Notice