Texas Instruments TNETX3270 PRODUCT PREVIEW

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999



POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•5

DA12–DA0

MRESET

ECLK

EDIO

DD31–DD0

DCLK

DRAS

DCAS

DW

LEDDATA

LEDCLK

SDATA7–SDATA0

SAD1–SAD0

SRNW

SCS

SRDY

DRAM

Port

LED

Activity

Port

CPU

Interface

Serial

MII

Interface

TH0CLK

TRST

TMS

TCLK

TDI

TDO

TAP

Address

Compare

Statistics

Storage

MIB

JTAG

Test Access

Port (TAP)

EEPROM

Port

TH0TXD3–TH0TXD0

TH0TXEN

TH0COL

TH0CRS

TH0SYNC

TH0RXD3–TH0RXD0

TH0RXDV

TH0LINK

MxxTCLK

MxxTXD3–MxxTXD0

MxxTXEN

MxxTXER

MxxCOL

MxxCRS

MxxRCLK

MxxRXD3–MxxRXD0

MxxRXDV

Three Ports

(24–26)†

10/100 Mbit/s

MxxRXER

MxxFORCE10

MxxFORCEHD

MxxLINK

MDCLK

MDIO

Network

Statistics

Logic

†xx is the port number that is being monitored.

Data Path

LED

Interface

TH0RENEG

TH1CLK

TH1TXD3–TH1TXD0

TH1TXEN

TH1COL

TH1CRS

TH1SYNC

TH1RXD3–TH1RXD0

TH1RXDV

TH1LINK

TH1RENEG

TH2CLK

TH2TXD3–TH2TXD0

TH2TXEN

TH2COL

TH2CRS

TH2SYNC

TH2RXD3–TH2RXD0

TH2RXDV

TH2LINK

TH2RENEG

CPU

Interface

SDRAM

Controller

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

MUX MUX MUX

Controller (MAC)

Controller (MAC)

MII

MII

MII

Eight Ports

(16–23)

10 Mbit/s

Eight Ports

(08–15)

10 Mbit/s

Eight Ports

(00–07)

10 Mbit/s

Queue

Manager

EEPROM

Interface

SDMA

SINT

STXRDY

SRXRDY

Miscellaneous

Functions OSCIN

RESET

MII

Figure 1. TNETX3270 Interface Block Diagram

PRODUCT PREVIEW

Contents

Main TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS description TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B NOVEMBER 1997 REVISED APRIL 1999 PGV PACKAGE (TOP VIEW) ThunderSWITCH 24/3 ETHERNET SWITCH PRODUCT PREVIEW Figure 1. TNETX3270 Interface Block Diagram Page TNETX3270 10-/100-Mbit/s MAC interface (ports 2426) 10-/100-Mbit/s MAC interface (ports 2426) (continued) SDRAM interface WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS host DIO interface serial MII management PHY interface EEPROM interface LED interface JTAG interface miscellaneous power interface summary of signal terminals by signal group function DIO register groups Table 1. Internal Register and Statistics Memory Map Table 2. Detailed DIO Register Map Page Page Page interface description receiving/transmitting management frames state of DIO signals during hardware reset network management port Page Page receive control giant (long) frames short frames receive filtering of frames data transmission transmit control adaptive performance optimization (APO) (transmit pacing) interframe gap enforcement ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS receive versus transmit priority uplink pretagging Table 5. Source-Port Pretag Encoding Page TNETX3270 interaction of EEPROM load with the SIO register summary of EEPROM load outcomes compatibility with future device revisions HIGHZ instruction lamp test multi-LED display hardware configurations Page TNETX3270 Figure 6. 10-Mbit/s Interface-Port Signal Timing Figure 7. Connecting to TNETE2008 PHY 10-/100-Mbit/s port configuration 10-/100-Mbit/s port configuration (continued) 10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch SDRAM interface (continued) Table 15. TNETX3270 Terminal Interface to SDRAMs SDRAM-type and quantity indication initialization refresh 39 frame routing txacc Figure 8. VLAN Overview Transmit rxacc IEEE Std 802.1Q headers reception IEEE Std 802.1Q headers transmission address maintenance spanning-tree support aging algorithms frame-routing determination Unkmem Figure 9. Frame-Routing Algorithm interrupt UnkVLAN Figure 9. Frame-Routing Algorithm (Continued) new chng secvio Port Trunking/Load Sharing port mirroring port trunking/load sharing collision-based flow control IEEE Std 802.3 flow control Page internal wrap test duplex wrap test Page absolute maximum ratings over operating junction temperature range (unless otherwise noted) recommended operating conditions electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MEASUREMENT INFORMATION test measurement 10-Mbit/s interface (ports 0023) timing requirements (see Notes 3 through 6 and Figure 13) Figure 13. 10-Mbit/s Interface (Ports 0023) 10-/100-Mbit/s MAC interface Figure 14. 10-/100-Mbit/s Receive Ports 10-/100-Mbit/s timing requirements (see Note 7 and Figure 14) 10-/100-Mbit/s timing requirements (see Figure 15) operating characteristics over recommended operating conditions (see Note 8 and Figure 15) Figure 15. 10-/100-Mbit/s Transmit Ports SDRAM interface SDRAM subcycle operating characteristics over recommended operating conditions (see Figure 17) Figure 17. SDRAM Subcycle DIO/DMA interface Figure 18. DIO/DMA Write Cycle timing requirements (see Figure 18) operating characteristics over recommended operating conditions (see Figure 18) DIO/DMA read cycle timing requirements (see Figure 19) Figure 19. DIO/DMA Read Cycle operating characteristics over recommended operating conditions (see Figure 19) serial MII management interface timing requirements (see Figure 20) operating characteristics over recommended operating conditions (see Figure 20) Figure 20. Serial MII Management Read/Write Cycle EEPROM interface operating characteristics over recommended operating conditions (see Figure 21) Figure 21. EEPROM LED interface operating characteristics over recommended operating conditions (see Figure 22) Figure 22. LED power-up OSCIN and RESET timing requirements (see Figure 23) Figure 23. Power-Up OSCIN and RESET MECHANICAL DATA PGV (S-PQFP-G240) PLASTIC QUAD FLATPACK (DIEDOWN)