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Texas Instruments TNETX3270 VLAN1QID VLAN0QID, VLAN3QID VLAN2QID, VLAN5QID VLAN4QID, VLAN10QID

Models: TNETX3270

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							TNETX3270
				ThunderSWITCH		24/3 ETHERNET SWITCH
			WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
				SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

		Table 2. Detailed DIO Register Map (Continued)

BYTE 3		BYTE 2		BYTE 1		BYTE 0	DIO
BYTE 3		BYTE 2		BYTE 1		BYTE 0	ADDRESS
							ADDRESS

		Reserved (for EEPROM CRC)					0x00FC

			VLAN0ports				0x0100

			VLAN1ports				0x0104

			VLAN2ports				0x0108

			VLAN3ports				0x010C

			VLAN4ports				0x0110

			VLAN5ports				0x0114

			VLAN6ports				0x0118

			VLAN7ports				0x011C

			VLAN8ports				0x0120

			VLAN9ports				0x0124

			VLAN10ports				0x0128

			VLAN11ports				0x012C

			VLAN12ports				0x0130

			VLAN13ports				0x0134

			VLAN14ports				0x0138

			VLAN15ports				0x013C

			VLAN16ports				0x0140

			VLAN17ports				0x0144

			VLAN18ports				0x0148

			VLAN19ports				0x014C

			VLAN20ports				0x0150

			VLAN21ports				0x0154

			VLAN22ports				0x0158

			VLAN23ports				0x015C

			VLAN24ports				0x0160

			VLAN25ports				0x0164

			VLAN26ports				0x0168

			VLAN27ports				0x016C

			VLAN28ports				0x0170

			VLAN29ports				0x0174

			VLAN30ports				0x0178

			VLAN31ports				0x017C

			Reserved				0x0180:0x02FF

VLAN1QID				VLAN0QID			0x0300

VLAN3QID				VLAN2QID			0x0304

VLAN5QID				VLAN4QID			0x0308

VLAN7QID				VLAN6QID			0x030C

VLAN9QID				VLAN8QID			0x0310

VLAN11QID				VLAN10QID			0x0314

VLAN13QID				VLAN12QID			0x0318

VLAN15QID				VLAN14QID			0x031C

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Image 15

Texas Instruments TNETX3270 VLAN1QID VLAN0QID, VLAN3QID VLAN2QID, VLAN5QID VLAN4QID, VLAN7QID VLAN6QID, VLAN9QID VLAN8QID

Contents

With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit controlUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±26Speed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice