TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999
DIO/DMA interface
The DIO interface is asynchronous to allow easy adaptation to a range of microprocessor devices and computer system interfaces.
DIO/DMA write cycle
timing requirements (see Figure 18)
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| MIN MAX | UNIT |
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1 | tw(SCSL) | Pulse duration, |
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| low | 24 | ns | ||||||||||
SCS |
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2 | tw(SCSH) | Pulse duration, |
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| high | 12 | ns | |||||||||
SCS | ||||||||||||||||||
3 | tsu(SRNW) | Setup time, |
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| low before |
| ↓ | 0 | ns | ||||||||
SRNW | SCS | |||||||||||||||||
4 | tsu(SAD) | Setup time, SAD1±SAD0 and |
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| valid before |
| ↓ | 0 | ns | ||||||||
SDMA | SCS | |||||||||||||||||
5 | tsu(SDATA) | Setup time, SDATA7±SDATA0 valid before |
| ↓ | 0 | ns | ||||||||||||
SCS | ||||||||||||||||||
operating characteristics over recommended operating conditions (see Figure 18)
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| PARAMETER | MIN | MAX | UNIT | |||||
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6 | tw(SRDYH) | Pulse duration, |
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| high |
| 12 | ns | |||||||||
SRDY |
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7 | td(SRNW) | Delay time, from |
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| ↓ to |
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| ↑ | 0 |
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SRDY | SRNW |
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8 | td(SAD) | Delay time, from |
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| ↓ to SAD1±SAD0 and |
| invalid | 0 |
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SRDY | SDMA |
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9 | td(SDATA) | Delay time, from |
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| ↓ to SDATA7±SDATA0 invalid | 0 |
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SRDY |
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10 | td(SCS) | Delay time, from |
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| ↓ to |
| ↑ | 0 |
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SRDY | SCS |
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11 | td(SRDY)1 | Delay time, from |
| ↓ to |
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| ↑ | 0 |
| ns | |||||||||
SCS | SRDY |
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12 | t | Delay time, from |
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| ↓ to |
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| ↓² | 0 |
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SCS | SRDY |
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| d(SRDY)2 |
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13 | td(SRDY)3 | Delay time, from |
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| ↑ | 0 | 24 | ns | ||||||||
SCS | SRDY | |||||||||||||||||||
²When the switch is performing certain internal operations (e.g., EEPROM load), there may be a considerable delay (approximately 25±100 ms) between SCS being asserted and SRDY being asserted.
5 |
| 12 |
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4 |
| 1 | 2 |
3 | 11 | 10 | 13 |
SCS (input)
7
SRNW (input)
8
SAD1±SAD0,
SDMA (inputs)
| 9 |
SDATA7± Z | Z |
SDATA0 |
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(inputs) | 6 |
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SRDY | Z |
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(output) |
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Figure 18. DIO/DMA Write Cycle
58 | POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
