Texas Instruments TNETX3270 SDRAM interface

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

SDRAM interface

TERMINAL

I/O

INTERNAL

DESCRIPTION

NAME NO.

I/O

RESISTOR

DESCRIPTION

DA13

DA12

DA11

DA10

DA09

DA08

DA07

DA06

DA05

DA04

DA03

DA02

DA01

DA00

212

210

209

207

206

205

204

203

202

200

199

198

196

195

O None SDRAM address bus (time-multiplexed bank, row, and column address). The address bus

DA13–DA00 also provides the SDRAM mode register initialization value. DA13 is the most significant

bit and DA00 is the least significant bit.

DCAS 189 O None SDRAM column address strobe. DCAS, in conjunction with DRAS and DW, determines the SDRAM

commands.

DCLK 193 O None SDRAM clock (83.33-MHz clock to the SDRAMs). SDRAM commands, addresses, and data are

sampled by the SDRAM on the rising edge of this clock.

DD31

DD30

DD29

DD28

DD27

DD26

DD25

DD24

DD23

DD22

DD21

DD20

DD19

DD18

DD17

DD16

DD15

DD14

DD13

DD12

DD11

DD10

DD09

DD08

DD07

DD06

DD05

DD04

DD03

DD02

DD01

DD00

187

186

185

183

182

181

180

179

177

176

174

173

172

171

170

168

167

166

164

162

161

159

158

157

156

155

153

152

150

149

147

146

I/O Pullup SDRAM data bus (bidirectional bus used to carry SDRAM data). DD31–DD00 also output status

information to indicate buffer operation type and port number. Internal pullup resistors are provided.

DD31 is the most significant bit and the DD00 is the least significant bit.

DRAS 190 O None SDRAM row address strobe. DRAS, with DCAS and DW, supplies the SDRAM commands.

DW 191 O None SDRAM write select. DW, with DRAS and DCAS, supplies the SDRAM commands.

Contents

Main TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS description TNETX3270 ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS ThunderSWITCH24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B NOVEMBER 1997 REVISED APRIL 1999 PGV PACKAGE (TOP VIEW) ThunderSWITCH 24/3 ETHERNET SWITCH PRODUCT PREVIEW Figure 1. TNETX3270 Interface Block Diagram Page TNETX3270 10-/100-Mbit/s MAC interface (ports 2426) 10-/100-Mbit/s MAC interface (ports 2426) (continued) SDRAM interface WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS host DIO interface serial MII management PHY interface EEPROM interface LED interface JTAG interface miscellaneous power interface summary of signal terminals by signal group function DIO register groups Table 1. Internal Register and Statistics Memory Map Table 2. Detailed DIO Register Map Page Page Page interface description receiving/transmitting management frames state of DIO signals during hardware reset network management port Page Page receive control giant (long) frames short frames receive filtering of frames data transmission transmit control adaptive performance optimization (APO) (transmit pacing) interframe gap enforcement ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS receive versus transmit priority uplink pretagging Table 5. Source-Port Pretag Encoding Page TNETX3270 interaction of EEPROM load with the SIO register summary of EEPROM load outcomes compatibility with future device revisions HIGHZ instruction lamp test multi-LED display hardware configurations Page TNETX3270 Figure 6. 10-Mbit/s Interface-Port Signal Timing Figure 7. Connecting to TNETE2008 PHY 10-/100-Mbit/s port configuration 10-/100-Mbit/s port configuration (continued) 10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch SDRAM interface (continued) Table 15. TNETX3270 Terminal Interface to SDRAMs SDRAM-type and quantity indication initialization refresh 39 frame routing txacc Figure 8. VLAN Overview Transmit rxacc IEEE Std 802.1Q headers reception IEEE Std 802.1Q headers transmission address maintenance spanning-tree support aging algorithms frame-routing determination Unkmem Figure 9. Frame-Routing Algorithm interrupt UnkVLAN Figure 9. Frame-Routing Algorithm (Continued) new chng secvio Port Trunking/Load Sharing port mirroring port trunking/load sharing collision-based flow control IEEE Std 802.3 flow control Page internal wrap test duplex wrap test Page absolute maximum ratings over operating junction temperature range (unless otherwise noted) recommended operating conditions electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MEASUREMENT INFORMATION test measurement 10-Mbit/s interface (ports 0023) timing requirements (see Notes 3 through 6 and Figure 13) Figure 13. 10-Mbit/s Interface (Ports 0023) 10-/100-Mbit/s MAC interface Figure 14. 10-/100-Mbit/s Receive Ports 10-/100-Mbit/s timing requirements (see Note 7 and Figure 14) 10-/100-Mbit/s timing requirements (see Figure 15) operating characteristics over recommended operating conditions (see Note 8 and Figure 15) Figure 15. 10-/100-Mbit/s Transmit Ports SDRAM interface SDRAM subcycle operating characteristics over recommended operating conditions (see Figure 17) Figure 17. SDRAM Subcycle DIO/DMA interface Figure 18. DIO/DMA Write Cycle timing requirements (see Figure 18) operating characteristics over recommended operating conditions (see Figure 18) DIO/DMA read cycle timing requirements (see Figure 19) Figure 19. DIO/DMA Read Cycle operating characteristics over recommended operating conditions (see Figure 19) serial MII management interface timing requirements (see Figure 20) operating characteristics over recommended operating conditions (see Figure 20) Figure 20. Serial MII Management Read/Write Cycle EEPROM interface operating characteristics over recommended operating conditions (see Figure 21) Figure 21. EEPROM LED interface operating characteristics over recommended operating conditions (see Figure 22) Figure 22. LED power-up OSCIN and RESET timing requirements (see Figure 23) Figure 23. Power-Up OSCIN and RESET MECHANICAL DATA PGV (S-PQFP-G240) PLASTIC QUAD FLATPACK (DIEDOWN)