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STATUS BYTE
Status byte when read by serial poll
*SRE
*SRE?
Register
Read/Write
Commands
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| Status Byte Register |
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| d7 | d6 | d5 | d4 | d3 | d2 | d1 | d0 | ||||
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| <erb> | <mss> | <esb> | <mav> | <hsb> | <csb> | <ssb> | - |
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Service
Request
Generation
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| e7 | e6 | e5 | e4 | e3 | e2 |
| e1 | e0 |
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| d7 | d6 | d5 | d4 | d3 | d2 | d1 | d0 | ||
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| Service Request Enable Register# |
| C0074 |
#Bit 6 in this register ignores data sent by *SRE and always returns 0 in response to *SRE?
<erb> | is a device defined queue summary bit indicating that the error queue is |
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<rqs> | is set by a request for service and is cleared by the poll. |
<esb> | is the standard event register summary bit. |
<mav> | is 'message available' indicating that the output queue is |
<hsb> | is 'hardware status' summary bit |
<csb> | is 'coupling status' summary bit |
<ssb> | is 'instrument status' summary bit |
<rqs>, <esb> and <mav> are defined in IEEE 488.2
<rqs> (request for service) will produce an SRQ at the controller. It is set by a change to either the Status Byte or the Service Enable Register that results in a New Reason for Service. It is cleared when <mss> goes FALSE (i.e. no reason for service) or by Serial Poll.