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Xilinx PCI-X v5.1 Conventions, Typographical, Preface About This Guide, Meaning or Use, Example

Models: PCI-X v5.1

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Preface: About This Guide

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Preface: About This Guide

Conventions

Typographical

The following typographical conventions are used in this document:

	Convention	Meaning or Use	Example

		Messages, prompts, and
	Courier font	program files that the system	speed grade: - 100
		displays

	Courier bold	Literal commands you enter in	ngdbuild design_name
	Courier bold	a syntactical statement	ngdbuild design_name

		Variables in a syntax	<design_name>
	angle brackets < >	statement for which you must
		supply values

		References to other manuals	See the Initiator/Target User
		References to other manuals	Guide for more information.
			Guide for more information.

	Italic font		If a wire is drawn so that it
		Emphasis in text	overlaps the pin of a symbol,
		Emphasis in text	the two nets are not
			the two nets are not
			connected.

		An optional entry or
	Square brackets [ ]	parameter. However, in bus	ngdbuild [option_name]
	Square brackets [ ]	specifications, such as	design_name
		specifications, such as	design_name
		bus[7:0], they are required.

	Braces { }	A list of items from which you	lowpwr ={onoff}
	Braces { }	must choose one or more	lowpwr ={onoff}
		must choose one or more

	Vertical bar	Separates items in a list of	lowpwr ={onoff}
	Vertical bar	choices	lowpwr ={onoff}
		choices

	Vertical ellipsis		IOB #1: Name = QOUT’
	Vertical ellipsis	Repetitive material that has	IOB #2: Name = CLKIN’
	.		IOB #2: Name = CLKIN’
	.		.
	.	been omitted	.
	.	been omitted	.
	.		.
	.		.
			.

	Horizontal ellipsis . . .	Omitted repetitive material	allow block block_name
			loc1 loc2... locn;

10	www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
		UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual Conventions, Typographical, Preface About This Guide, Meaning or Use, Example, Italic font

Contents

LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24Getting Started Guide Revision VersionPCI-X v5.1 165 Getting Started Guide UG158 March 24 Revision Versionug000preface.fm to “Guide.” Revision Updated tools for IP0K releaseVersion 10/10/07Chapter 1 Getting Started Table of ContentsPreface About This Guide Chapter 2 Licensing the CoreVerilog VHDL Exemplar LeonardoSpectrum Xilinx XST Chapter 6 Implementing a DesignChapter 7 Timing Simulation ISE FoundationChapter 4 Functional Simulation Chapter 5 Synthesizing a Design Schedule of FiguresChapter 1 Getting Started Chapter 2 Licensing the Core Chapter 6 Implementing a Design Chapter 7 Timing SimulationPCI-X v5.1 165 Getting Started Guide UG158 March 24About This Guide Guide ContentsPreface Preface About This Guide ConventionsTypographical ConventionSee “Additional Resources” Online DocumentConventions Blue textPCI-X v5.1 165 Getting Started Guide Preface About This GuideUG158 March 24 System Requirements Getting StartedChapter About the Example DesignFeedback Additional DocumentationTechnical Support Core Interface for PCI-XLicensing Options Licensing the CoreBefore you Begin Full System Hardware EvaluationDirect Download Installing Your License FileFull License Obtaining a Full LicenseTable 3-1 Device and Interface Selection Family Specific ConsiderationsDesign Support Supported DeviceTable 3-1 Device and Interface Selection Chapter 3 Family Specific ConsiderationsWrapper File Supported DeviceSupported Device Design Support Table 3-1 Device and Interface SelectionWrapper File Bus TypeChapter 3 Family Specific Considerations Wrapper FilesConstraints Files Table 3-1 Device and Interface SelectionDevice Initialization Configuration PinsBus Mode Detection Bus Width DetectionDesired System Interface Implementation Bus Clock UsageTable 3-2 Bitstream Requirements BitstreamsElectrical Compliance 3.6 volts, as allowed by the PCI Local Bus SpecificationElectrical Compliance Figure 3-1 PCI/PCI-X Output Driver VCCO GenerationInput Delay Buffers Chapter 3 Family Specific ConsiderationsGenerating Bitstreams Generating BitstreamsPCI-X v5.1 165 Getting Started Guide Chapter 3 Family Specific ConsiderationsUG158 March 24 Cadence IUS Functional SimulationChapter Verilog Mentor Graphics ModelSimChapter 4 Functional Simulation VHDL Mentor Graphics ModelSimChapter 4 Functional Simulation vlib simprimFigure 5-1 Create a New Project Synthesizing a DesignSynplicity Synplify ChapterChapter 5 Synthesizing a Design Figure 5-2 Main Project WindowFigure 5-3 Files to Add Virtex Library Synplicity SynplifyFigure 5-4 Files to Add LogiCORE Files Chapter 5 Synthesizing a Design Figure 5-5 Files to Add User ApplicationFigure 5-6 Source Files in Main Project Window 7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click Add10. Click Change Result File to display the EDIF Result File dialog box then move the to following directory Figure 5-7 Options for Implementation DeviceSynplicity Synplify Figure 5-8 Options for Implementation Options/ConstraintsVHDL Figure 5-9 Create a New ProjectInstall Path/vhdl/example/synthesis Chapter 5 Synthesizing a DesignSynplicity Synplify Figure 5-10 Main Project WindowFigure 5-11 Files to Add Virtex Library 3. Click OK to exit the dialog and return to the project window FigureInstall Path/vhdl/src/xpci Figure 5-12 Files to Add LogiCORE FilesFigure 5-13 Files to Add User Application Install Path/vhdl/example/sourceSynplicity Synplify Figure 5-14 Main Project Window8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure Figure 5-15 Options for Implementation Device Exemplar LeonardoSpectrumChapter 5 Synthesizing a Design Xilinx XST Xilinx XSTPCI-X v5.1 165 Getting Started Guide Chapter 5 Synthesizing a DesignUG158 March 24 ISE Foundation Implementing a DesignChapter Chapter 6 Implementing a Design Chapter Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/*.v Cadence IUSVerilog Chapter 7 Timing SimulationMentor Graphics ModelSim VHDLInstall Path/vhdl/example/postsim Mentor Graphics ModelSim