5Files to Add User Application | Xilinx PCI-X v5.1 guide

R

Chapter 5: Synthesizing a Design

7.Navigate to the source directory (Figure 5-5), select the cfg_test_s.v, pcix_top.v, and userapp.v files, and then click Add.

Figure 5-5:Files to Add (User Application)

8.After adding the three final files (for a total of six source files), click OK to return to the main project window.

9.In the Source Files list, view the list of newly added source files by double-clicking the flowtest/verilog folder (if it is not already open). Reorder the source files in the folder by dragging them to list them in the hierarchical order displayed in Figure 5-6.

Figure 5-6:Source Files in Main Project Window

34	www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
		UG158 March 24, 2008

Image 34

Xilinx PCI-X v5.1 manual 5Files to Add User Application

Contents

LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24 PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version Revision Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/Constraints PCI-X v5.1 165 Getting Started Guide Guide Contents About This Guide Preface About This Guide ConventionsTypographical Convention Meaning or Use Example Online Document Conventions Preface About This Guide System Requirements Getting StartedAbout the Example Design Feedback Additional DocumentationTechnical Support Core Interface for PCI-X Licensing Options Licensing the CoreBefore you Begin Full System Hardware Evaluation Direct Download Installing Your License FileFull License Licensing the Core Family Specific Considerations Design Support Simulation Virtex-4 Devices Wrapper Files Device Initialization Configuration PinsBus Mode Detection Bus Width Detection Bus Clock Usage Family Specific Considerations Electrical Compliance Electrical Compliance Input Delay Buffers Generating Bitstreams Generating Bitstreams Family Specific Considerations Functional Simulation Cadence IUS Verilog Mentor Graphics ModelSimFunctional Simulation Install Path/verilog/example/funcsim Mentor Graphics ModelSim To run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity Synplify Synthesizing a Design 2Main Project Window Synplicity Synplify 3Files to Add Virtex Library 5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation Device Xilinx XST Xilinx XST Synthesizing a Design Implementing a Design ISE Foundation Implementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim