Manuals / Xilinx / Computer Equipment / Computer Hardware

Xilinx PCI-X v5.1 Family Specific Considerations, Design Support, Supported Device, Bus Type

Models: PCI-X v5.1

1 47

Download 47 pages 38.14 Kb

Page 17

Family Specific Considerations

R

Chapter 3

Family Specific Considerations

This chapter provides important design information specific to the core interface targeting Virtex devices.

Design Support

Table 3-1provides a list of supported device and interface combinations, consisting of a device, a bus interface type, and two or three specific implementation files.

Table 3-1:Device and Interface Selection

Supported Device

Bus Type

Wrapper File

Simulation

Model

Constraints File

Virtex-E Devices

V300E-BG432-8C	33 MHz PCI	pcix_lc_64ne	v300ebg432_64n.ucf
	3.3V 64-bit	pcix_core

V300E-BG432-8C	66 MHz PCI-X	pcix_lc_64xe	v300ebg432_64x.ucf
	3.3V 64-bit	pcix_core

	Virtex-II Devices

2V1000-FG456-5C/I	33 MHz PCI	pcix_lc_64n	2v1000fg456_64n.ucf
	3.3V 64-bit	pcix_core

2V1000-FG456-5C/I	66 MHz PCI-X	pcix_lc_64x	2v1000fg456_64x.ucf
	3.3V 64-bit	pcix_core

2V1000-FG456-5C/I	100 MHz PCI-X	pcix_lc_64xf	2v1000fg456_64xf.ucf
	3.3V 64-bit	pcix_fast

2V1000-FG456-6C/I	133 MHz PCI-X	pcix_lc_64xf	2v1000fg456_64xf.ucf
	3.3V 64-bit	pcix_fast

2V1000-FG456-5C/I	33 MHz PCI	pcix_lc_64s	2v1000fg456_64s.ucf
	66 MHz PCI-X	pcix_core
	3.3V 64-bit

	Virtex-II Pro Devices

2VP7-FF672-6C/I

33 MHz PCI

3.3V 64-bit

pcix_lc_64n pcix_core

2vp7ff672_64n.ucf

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

17

UG158 March 24, 2008

Image 17

Xilinx PCI-X v5.1 manual Family Specific Considerations, Design Support, 1 Device and Interface Selection, Supported Device

Contents

Getting Started Guide UG158 March 24LogiCORE IP Initiator/Target v5.1 for PCI-X PCI-X v5.1 165 Getting Started Guide UG158 March 24 VersionRevision ug000preface.fm to “Guide.” VersionRevision Version Updated tools for IP0K releaseRevision 10/10/07Preface About This Guide Table of ContentsChapter 1 Getting Started Chapter 2 Licensing the CoreChapter 7 Timing Simulation Chapter 6 Implementing a DesignVerilog VHDL Exemplar LeonardoSpectrum Xilinx XST ISE FoundationChapter 1 Getting Started Chapter 2 Licensing the Core Schedule of FiguresChapter 4 Functional Simulation Chapter 5 Synthesizing a Design Chapter 6 Implementing a Design Chapter 7 Timing SimulationUG158 March 24 PCI-X v5.1 165 Getting Started GuidePreface Guide ContentsAbout This Guide Typographical ConventionsPreface About This Guide ConventionConventions Online DocumentSee “Additional Resources” Blue textUG158 March 24 Preface About This GuidePCI-X v5.1 165 Getting Started Guide Chapter Getting StartedSystem Requirements About the Example DesignTechnical Support Additional DocumentationFeedback Core Interface for PCI-XBefore you Begin Licensing the CoreLicensing Options Full System Hardware EvaluationFull License Installing Your License FileDirect Download Obtaining a Full LicenseDesign Support Family Specific ConsiderationsTable 3-1 Device and Interface Selection Supported DeviceWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Supported DeviceWrapper File Design Support Table 3-1 Device and Interface SelectionSupported Device Bus TypeConstraints Files Wrapper FilesChapter 3 Family Specific Considerations Table 3-1 Device and Interface SelectionBus Mode Detection Configuration PinsDevice Initialization Bus Width DetectionTable 3-2 Bitstream Requirements Bus Clock UsageDesired System Interface Implementation BitstreamsElectrical Compliance 3.6 volts, as allowed by the PCI Local Bus SpecificationElectrical Compliance Figure 3-1 PCI/PCI-X Output Driver VCCO GenerationChapter 3 Family Specific Considerations Input Delay BuffersGenerating Bitstreams Generating BitstreamsUG158 March 24 Chapter 3 Family Specific ConsiderationsPCI-X v5.1 165 Getting Started Guide Chapter Functional SimulationCadence IUS Chapter 4 Functional Simulation Mentor Graphics ModelSimVerilog Mentor Graphics ModelSim VHDLvlib simprim Chapter 4 Functional SimulationSynplicity Synplify Synthesizing a DesignFigure 5-1 Create a New Project ChapterFigure 5-2 Main Project Window Chapter 5 Synthesizing a DesignFigure 5-4 Files to Add LogiCORE Files Synplicity SynplifyFigure 5-3 Files to Add Virtex Library Figure 5-6 Source Files in Main Project Window Figure 5-5 Files to Add User ApplicationChapter 5 Synthesizing a Design 7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click AddSynplicity Synplify Figure 5-7 Options for Implementation Device10. Click Change Result File to display the EDIF Result File dialog box then move the to following directory Figure 5-8 Options for Implementation Options/ConstraintsInstall Path/vhdl/example/synthesis Figure 5-9 Create a New ProjectVHDL Chapter 5 Synthesizing a DesignFigure 5-11 Files to Add Virtex Library Figure 5-10 Main Project WindowSynplicity Synplify 3. Click OK to exit the dialog and return to the project window FigureFigure 5-13 Files to Add User Application Figure 5-12 Files to Add LogiCORE FilesInstall Path/vhdl/src/xpci Install Path/vhdl/example/source8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure Figure 5-14 Main Project WindowSynplicity Synplify Chapter 5 Synthesizing a Design Exemplar LeonardoSpectrumFigure 5-15 Options for Implementation Device Xilinx XST Xilinx XSTUG158 March 24 Chapter 5 Synthesizing a DesignPCI-X v5.1 165 Getting Started Guide Chapter Implementing a DesignISE Foundation Chapter 6 Implementing a Design cd Install Path/verilog/example/postsim cp ../xilinx/*.v Timing SimulationChapter Cadence IUSMentor Graphics ModelSim Chapter 7 Timing SimulationVerilog VHDLMentor Graphics ModelSim Install Path/vhdl/example/postsim