Xilinx PCI-X v5.1 manual About This Guide, Guide Contents

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Preface

About This Guide

The Initiator/Target v5.1 for PCI-X Getting Started Guide provides information about the LogiCORE™ IP interface core for Peripheral Component Interconnect Extended (PCI-X), which provides a fully verified, pre-implementedPCI-X bus interface targeting devices based on the Virtex™ FPGA architecture.

The guide also includes an example design in both Verilog-HDL and VHDL that lets you simulate, synthesize, and implement the interface to understand the design flow for PCI-X.

Guide Contents

This manual contains the following chapters:

•Chapter 1, “Getting Started,”describes the Initiator/Target core for PCI-X and provides information about getting technical support, and providing feedback to Xilinx about the core and the accompanying documentation.

•Chapter 2, “Licensing the Core,” provides instructions for installing and obtaining a license for the core interface, which you must do before using it in your designs.

•Chapter 3, “Family Specific Considerations,” discusses design considerations specific to the core interface targeting Virtex devices.

•Chapter 4, “Functional Simulation,” describes the use of supported functional simulation tools, including Cadence® IUS and Mentor Graphics® ModelSim®.

•Chapter 5, “Synthesizing a Design,” describes the use of supported synthesis tools, including Synplicity Synplify, Exemplar LeonardoSpectrum, and Xilinx XST.

•Chapter 6, “Implementing a Design,” describes the use of supported FPGA implementation tools, included with the Xilinx ISE™ Foundation v10.1 software.

•Chapter 7, “Timing Simulation,” describes the use of supported post-route timing simulation tools, including Cadence IUS and Mentor Graphics ModelSim.

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 9

UG158 March 24, 2008